公开(公告)号：US11699633B1

公开(公告)日：2023-07-11

申请号：US18148986

申请日：2022-12-30

申请人： Beijing University of Technology

发明人： Tong An ,  Rui Zhou ,  Yakun Zhang ,  Fei Qin

IPC分类号： H01L23/40 ,  H01L23/473 ,  F16F15/04

CPC分类号： H01L23/4006 ,  H01L23/473 ,  F16F15/04 ,  H01L2023/4025 ,  H01L2023/4081 ,  H01L2023/4087

摘要： Disclosed is a pressure balancing clamp for a press-pack insulated gate bipolar transistor (IGBT) module. The pressure balancing clamp for a press-pack IGBT module includes a bracket, where the bracket is provided with two longitudinally arranged pressure equalizing plates in a sliding way; the pressure equalizing plates are connected through pressure sensors; the upper and lower ends inside the bracket are respectively connected with the pressure equalizing plates through hydraulic devices and a displacement compensation device; opposite surfaces of the two pressure equalizing plates are respectively provided with heat dissipation and confluence devices. The pressure sensors are in one-to-one correspondence with the hydraulic devices and are electrically connected. The hydraulic devices adjust the pressure according to the readings of the pressure sensors in corresponding directions, so that the pressure of the press-pack IGBT module is balanced.

公开(公告)号：US11251106B2

公开(公告)日：2022-02-15

申请号：US17219788

申请日：2021-03-31

申请人： BEIJING UNIVERSITY OF TECHNOLOGY

发明人： Fei Qin ,  Shuai Zhao ,  Yanwei Dai ,  Pei Chen ,  Tong An

IPC分类号： H01L23/373 ,  H01L23/15 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L29/16

摘要： The invention discloses a packaging structure and manufacturing method of a SiC MOSFET module, which is composed of SiC MOSFET chips, upper DBC substrate, lower DBC substrate, ceramic interposer, silicon oxide dielectric layer, nano silver pastes, redistribution layer, through-ceramic-hole conductive metals and power terminals. The SiC MOSFET chips are connected to the lower DBC substrate using nano silver pastes in the invention. Besides, some rectangular frames are made on the ceramic interposer, and the SiC MOSFET chips are embedded in the ceramic interposer by filling dielectric materials. The upper surfaces of the chips and the ceramic interposer are covered with a conductive metal redistribution layer, and the upper and lower surfaces of the ceramic interposer are interconnected with the upper and lower DBC substrates, respectively. The power terminals are led out from the conductive copper layers of the upper and lower DBC substrates. This invention can realize the high-temperature packaging of SiC MOSFET modules. By introducing double-sided heat dissipation, the thermal performance can be improved effectively. The parasitic inductance of the module can be also reduced by using planar interconnection instead of wire bonding.

公开(公告)号：US11698248B1

公开(公告)日：2023-07-11

申请号：US18073713

申请日：2022-12-02

申请人： Beijing University of Technology

发明人： Tong An ,  Xueheng Zheng ,  Rui Zhou ,  Fei Qin

IPC分类号： G01B11/02 ,  H01L21/67 ,  G01B11/30 ,  G01M5/00 ,  G01M99/00 ,  G01N3/56

CPC分类号： G01B11/02 ,  G01B11/026 ,  G01B11/30 ,  G01M5/0033 ,  G01M5/0041 ,  G01M99/002 ,  G01N3/56 ,  H01L21/67259 ,  H01L21/67288

摘要： Disclosed are a device and a method for measuring a fretting displacement in a power cycling of a press-pack insulated gate bipolar transistor (IGBT). The IGBT includes: a bracket; slide bars slidably mounted on the bracket and are arranged at least four along a circumferential direction of the bracket; sensors respectively slidably installed on the bracket and the slide bars; and a power cycling experiment device arranged inside the bracket.

公开(公告)号：US20210407863A1

公开(公告)日：2021-12-30

申请号：US16483027

申请日：2018-10-30

申请人： Beijing University of Technology

发明人： Fei Qin ,  Lixiang Zhang ,  Shuai Zhao ,  Pei Chen ,  Tong An ,  Yanwei Dai

IPC分类号： H01L21/66 ,  B24B7/22 ,  B24B49/04 ,  H01L21/306 ,  H01L21/67

摘要： A method and apparatus for on-line measurement of the wafer thinning and grinding force, related to the field of ultra-precision machining of semiconductor wafer materials. The grinding force measuring apparatus comprises a semiconductor wafer, a worktable, a bearing table, a thin film pressure sensor, and a data processing and wireless transmission module. The grinding force measuring method includes sensor calibration based on the testing device and on-line measurement of grinding force. Using the grinding force measuring device and method provided by the invention, the grinding force in the semiconductor wafer grinding process can be monitored in real time, which is of great significance for semiconductor processing and reducing grinding damage. The invention also has the following characteristics: the sensor adopts a film pressure sensor, the response time is short, and the test precision is high; the data transmission adopts a wireless transmission design, thus the grinding force can be monitored in real time during the wafer and spindle rotation process and the risk of winding during wafer rotation can be avoided. The sensor adopts a distributed design, which can monitor the distribution of the grinding force along the wafer radial direction or crystal orientation.

公开(公告)号：US20140302640A1

公开(公告)日：2014-10-09

申请号：US14354592

申请日：2012-12-04

申请人： BEIJING UNIVERSITY OF TECHNOLOGY

发明人： Fei Qin ,  Guofeng Xia ,  Tong An ,  Chengyan Liu ,  Wei Wu ,  Wenhui Zhu

IPC分类号： H01L21/48 ,  H01L21/56

CPC分类号： H01L21/4828 ,  H01L21/4825 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/49861 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92127 ,  H01L2224/92242 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45664

摘要： A manufacturing method for Flip Chip on Chip (FCoC) package based on multi-row Quad Flat No-lead (QFN) package is provided wherein the lower surface of plate metallic base material are half-etched to form grooves. Insulation filling material is filled in the half-etched grooves. The upper surface of plate metallic base material is half-etched to form chip pad and multi-row of leads. Encapsulating first IC chip, second IC chip, solder bumps, underfill material, and metal wire to form an array of FCoC package based on the type of multi-row QFN package. Sawing and separating the FCoC package array, and forming FCoC package unit.

摘要翻译： 提供了一种基于多行四边形扁平无引线（QFN）封装的倒装芯片（FCoC）封装的制造方法，其中板金属基材的下表面被半蚀刻以形成凹槽。 绝缘填充材料填充在半蚀刻槽中。 板金属基材的上表面被半刻蚀以形成芯片焊盘和多排引线。 封装第一个IC芯片，第二个IC芯片，焊料凸块，底部填充材料和金属线，以形成基于多行QFN封装类型的FCoC封装阵列。 锯切和分离FCoC封装阵列，并形成FCoC封装单元。