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    METHOD FOR TREATING A WAFER EDGE
    1.
    发明申请
    METHOD FOR TREATING A WAFER EDGE 审中-公开
    用于处理波峰的方法

    公开(公告)号：US20090004865A1

    公开(公告)日：2009-01-01

    申请号：US11770792

    申请日：2007-06-29

    申请人： Bernd E. E. Kastenmeier ,  Andreas Knorr

    发明人： Bernd E. E. Kastenmeier ,  Andreas Knorr

    IPC分类号： H01L21/31

    CPC分类号： H01L21/02087 ,  H01L21/31053 ,  H01L21/6708 ,  H01L21/67086

    摘要： A method for treating an edge portion of a wafer with a plasma or select chemical formulation in order to enhance adhesion characteristics and inhibit delamination of a layer of material from the wafer surface only on the edge portion that is being treated. Alternatively, the method may be utilized to effectuate a cleaning of an edge portion of a wafer.

    摘要翻译： 一种用等离子体或选择的化学配方处理晶片的边缘部分的方法，以便仅在待处理的边缘部分上增强粘附特性并且抑制材料层从晶片表面的分层。 或者，该方法可用于实现晶片边缘部分的清洁。

    Semiconductor structures and methods for forming isolation between Fin structures of FinFET devices
    3.
    发明授权
    Semiconductor structures and methods for forming isolation between Fin structures of FinFET devices 有权
    用于在FinFET器件的Fin结构之间形成隔离的半导体结构和方法

    公开(公告)号：US09257325B2

    公开(公告)日：2016-02-09

    申请号：US12562849

    申请日：2009-09-18

    申请人： Andreas Knorr ,  Frank Scott Johnson

    发明人： Andreas Knorr ,  Frank Scott Johnson

    IPC分类号： H01L29/06 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78

    CPC分类号： H01L21/76229 ,  H01L29/66795 ,  H01L29/7851

    摘要： Semiconductor structures and methods for forming isolation between fin structures formed from a bulk silicon wafer are provided. A bulk silicon wafer is provided having one or more fin structures formed therefrom. Forming of the fin structures defines isolation trenches between the one or more fin structures. Each of the fin structures has vertical sidewalls. An oxide layer is deposited in the isolation trenches and on the vertical sidewalls using HDPCVD in about a 4:1 ratio or greater. The oxide layer is isotropically etched to remove the oxide layer from the vertical sidewalls and a portion of the oxide layer from the bottom of the isolation trenches. A substantially uniformly thick isolating oxide layer is formed on the bottom of the isolation trench to isolate the one or more fin structures and substantially reduce fin height variability.

    摘要翻译： 提供了用于形成由体硅晶片形成的翅片结构之间的隔离的半导体结构和方法。 提供具有由其形成的一个或多个翅片结构的体硅晶片。 翅片结构的形成限定了一个或多个翅片结构之间的隔离沟槽。 每个翅片结构都具有垂直侧壁。 使用HDPCVD以大约4:1的比例或更大的比例在隔离沟槽和垂直侧壁上沉积氧化物层。 氧化层被各向同性蚀刻以从隔离沟底部的垂直侧壁和氧化物层的一部分去除氧化物层。 在隔离沟槽的底部上形成基本上均匀的厚的隔离氧化物层，以隔离一个或多个翅片结构，并显着降低翅片高度的可变性。

    METHOD FOR SELF-ALIGNING A STOP LAYER TO A REPLACEMENT GATE FOR SELF-ALIGNED CONTACT INTEGRATION
    8.
    发明申请
    METHOD FOR SELF-ALIGNING A STOP LAYER TO A REPLACEMENT GATE FOR SELF-ALIGNED CONTACT INTEGRATION 有权
    将自动对准停止层的方法用于自对准接触集成的替换门

    公开(公告)号：US20110062501A1

    公开(公告)日：2011-03-17

    申请号：US12561708

    申请日：2009-09-17

    申请人： Steven R. Soss ,  Andreas Knorr

    发明人： Steven R. Soss ,  Andreas Knorr

    IPC分类号： H01L29/78 ,  H01L21/28

    CPC分类号： H01L29/4966 ,  H01L21/28114 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  Y10S438/926

    摘要： Semiconductor devices with replacement gate electrodes and integrated self aligned contacts are formed with enhanced gate dielectric layers and improved electrical isolation properties between the gate line and a contact. Embodiments include forming a removable gate electrode on a substrate, forming a self aligned contact stop layer over the removable gate electrode and the substrate, removing a portion of the self aligned contact stop layer over the removable gate electrode and the electrode itself leaving an opening, forming a replacement gate electrode of metal, in the opening, transforming an upper portion of the metal into a dielectric layer, and forming a self aligned contact. Embodiments include forming the contact stop layer of a dielectric material, e.g., a hafnium oxide, an aluminum oxide, or a silicon carbide and transforming the upper portion of the metal into a dielectric layer by oxidation, fluorination, or nitridation. Embodiments also include forming a hardmask layer over the removable gate electrode to protect the electrode during silicidation in source/drain regions of the semiconductor device.

    摘要翻译： 具有替换栅电极和集成自对准触点的半导体器件由栅极电介质层和栅极线与触点之间的电隔离特性提高而形成。 实施例包括在衬底上形成可移除的栅电极，在可移除的栅电极和衬底之上形成自对准的接触止动层，在可移除的栅极电极和电极本身上移除一部分自对准接触停止层，留下开口， 在开口中形成金属的替代栅电极，将金属的上部转化成电介质层，并形成自对准的接触。 实施例包括形成电介质材料例如氧化铪，氧化铝或碳化硅的接触停止层，并通过氧化，氟化或氮化将金属的上部转化成电介质层。 实施例还包括在可移除的栅极电极上形成硬掩模层，以在半导体器件的源极/漏极区域中的硅化期间保护电极。