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    JFET having width defined by trench isolation
    3.
    发明授权
    JFET having width defined by trench isolation 有权
    JFET具有由沟槽隔离限定的宽度

    公开(公告)号：US09076760B2

    公开(公告)日：2015-07-07

    申请号：US13597439

    申请日：2012-08-29

    申请人： Binghua Hu ,  Pinghai Hao ,  Sameer Pendharkar

    发明人： Binghua Hu ,  Pinghai Hao ,  Sameer Pendharkar

    IPC分类号： G01R31/26 ,  H01L29/417 ,  H01L21/00 ,  H01L29/423 ,  H01L29/808 ,  H01L29/06 ,  H01L29/10

    CPC分类号： H01L29/41725 ,  G06F2101/00 ,  G06F2201/00 ,  H01L21/00 ,  H01L29/0692 ,  H01L29/1066 ,  H01L29/42316 ,  H01L29/808

    摘要： A junction field-effect transistor (JFET) includes a substrate having a first-type semiconductor surface including a topside surface, and a top gate of a second-type formed in the semiconductor surface. A first-type drain and a first-type source are formed on opposing sides of the top gate. A first deep trench isolation region has an inner first trench wall and an outer first trench wall surrounding the top gate, the drain and the source, and extends vertically to a deep trench depth from the topside surface. A second-type sinker formed in semiconductor surface extends laterally outside the outer first trench wall. The sinker extends vertically from the topside surface to a second-type deep portion which is both below the deep trench depth and laterally inside the inner first trench wall to provide a bottom gate.

    摘要翻译： 结型场效应晶体管（JFET）包括具有包括顶侧表面的第一类型半导体表面的衬底和形成在半导体表面中的第二类型的顶栅。 第一型漏极和第一型源形成在顶栅的相对侧上。 第一深沟槽隔离区域具有围绕顶部栅极，漏极和源极的内部第一沟槽壁和外部第一沟槽壁，并且从顶侧表面垂直延伸到深沟槽深度。 形成在半导体表面中的第二类型沉降片在外部第一沟槽壁的外侧横向延伸。 沉降片从顶侧表面垂直延伸到第二类型深部，该深部位于深沟槽深度的下方并且在内部第一沟槽壁的横向内部以提供底部门。

    MOS TRANSISTOR WITH GATE TRENCH ADJACENT TO DRAIN EXTENSION FIELD INSULATION
    4.
    发明申请
    MOS TRANSISTOR WITH GATE TRENCH ADJACENT TO DRAIN EXTENSION FIELD INSULATION 有权
    具有栅极扩展的MOS晶体管与漏极扩展场绝缘相邻

    公开(公告)号：US20110111569A1

    公开(公告)日：2011-05-12

    申请号：US13006589

    申请日：2011-01-14

    申请人： Marie Denison ,  Sameer Pendharkar ,  Binghua Hu ,  Taylor Rice Efland ,  Sridhar Seetharaman

    发明人： Marie Denison ,  Sameer Pendharkar ,  Binghua Hu ,  Taylor Rice Efland ,  Sridhar Seetharaman

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7825 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66689 ,  H01L29/66704

    摘要： An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.

    摘要翻译： 一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的沟槽栅极。 体阱和源极扩散区域与栅极沟槽的底表面重叠。 一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的第一沟槽栅极和位于重掺杂掩埋层上方的第二沟槽栅极。 埋层是与漂移区相同的导电类型。 形成包含MOS晶体管的集成电路的过程，其包括在晶体管的漏极的漂移区上方的隔离电介质层和形成在栅极沟槽中的栅极，该栅极与隔离电介质层相邻。 通过去除与隔离电介质层相邻的衬底材料形成栅极沟槽。

    MOS transistor with gate trench adjacent to drain extension field insulation
    5.
    发明授权
    MOS transistor with gate trench adjacent to drain extension field insulation 有权
    MOS晶体管，栅极沟槽与漏极延伸场绝缘相邻

    公开(公告)号：US07893499B2

    公开(公告)日：2011-02-22

    申请号：US12417810

    申请日：2009-04-03

    申请人： Marie Denison ,  Sameer Pendharkar ,  Binghua Hu ,  Taylor Rice Efland ,  Sridhar Seetharaman

    发明人： Marie Denison ,  Sameer Pendharkar ,  Binghua Hu ,  Taylor Rice Efland ,  Sridhar Seetharaman

    IPC分类号： H01L29/66

    CPC分类号： H01L29/7825 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66689 ,  H01L29/66704

    摘要： An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.

    摘要翻译： 一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的沟槽栅极。 体阱和源极扩散区域与栅极沟槽的底表面重叠。 一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的第一沟槽栅极和位于重掺杂掩埋层上方的第二沟槽栅极。 埋层是与漂移区相同的导电类型。 形成包含MOS晶体管的集成电路的过程，其包括在晶体管的漏极的漂移区上方的隔离电介质层和形成在栅极沟槽中的栅极，该栅极与隔离电介质层相邻。 通过去除与隔离电介质层相邻的衬底材料形成栅极沟槽。

    MOS Transistor with Gate Trench Adjacent to Drain Extension Field Insulation
    6.
    发明申请
    MOS Transistor with Gate Trench Adjacent to Drain Extension Field Insulation 有权
    MOS晶体管，栅极沟槽与漏极延伸场绝缘相邻

    公开(公告)号：US20100252882A1

    公开(公告)日：2010-10-07

    申请号：US12417810

    申请日：2009-04-03

    申请人： Marie Denison ,  Sameer Pendharkar ,  Binghua Hu ,  Taylor Rice Efland ,  Sridhar Seetharaman

    发明人： Marie Denison ,  Sameer Pendharkar ,  Binghua Hu ,  Taylor Rice Efland ,  Sridhar Seetharaman

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7825 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66689 ,  H01L29/66704

    摘要： An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.

    摘要翻译： 一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的沟槽栅极。 体阱和源极扩散区域与栅极沟槽的底表面重叠。 一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的第一沟槽栅极和位于重掺杂掩埋层上方的第二沟槽栅极。 埋层是与漂移区相同的导电类型。 形成包含MOS晶体管的集成电路的过程，其包括在晶体管的漏极的漂移区上方的隔离电介质层和形成在栅极沟槽中的栅极，该栅极与隔离电介质层相邻。 通过去除与隔离电介质层相邻的衬底材料形成栅极沟槽。

    METHODS FOR PREPARING AND DEVICES WITH TREATED DUMMY MOATS
    7.
    发明申请
    METHODS FOR PREPARING AND DEVICES WITH TREATED DUMMY MOATS 有权
    用于制备和装置与处理的DUMMY MOATS的方法

    公开(公告)号：US20090166875A1

    公开(公告)日：2009-07-02

    申请号：US11968085

    申请日：2007-12-31

    申请人： SAMEER PENDHARKAR ,  Binghua Hu

    发明人： SAMEER PENDHARKAR ,  Binghua Hu

    IPC分类号： H01L23/48 ,  H01L21/44

    CPC分类号： H01L21/761 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0207

    摘要： Devices and methods are presented to fabricate dummy moats in an isolation region on a substrate. Presently, dummy moats are prone to losing impedance after the silicidation process. In high-voltage devices, silicided dummy moats reduce the breakdown voltage between active regions, particularly when the dummy moat overlaps or is in close proximity to a junction. The present devices and methods disclose a dummy moat covered with an oxide layer. During the silicidation process, the dummy moat and other designated isolation regions remain non-silicided. Thus, high and stable breakdown voltages are maintained.

    摘要翻译： 提供了设备和方法以在衬底上的隔离区域中制造虚设的护城河。 目前，在硅化处理之后，假山羊容易失去阻抗。 在高压设备中，硅化虚拟护城河降低了活性区域之间的击穿电压，特别是当虚拟护套重叠或接近结点时。 本发明的装置和方法公开了覆盖有氧化物层的虚拟护城河。 在硅化过程中，虚拟护城河和其他指定的隔离区域保持非硅化。 因此，保持高且稳定的击穿电压。

    Formation of a MOSFET Using an Angled Implant
    9.
    发明申请
    Formation of a MOSFET Using an Angled Implant 有权
    使用倾斜植入物形成MOSFET

    公开(公告)号：US20090294841A1

    公开(公告)日：2009-12-03

    申请号：US12509922

    申请日：2009-07-27

    申请人： Sameer Pendharkar ,  Binghua Hu

    发明人： Sameer Pendharkar ,  Binghua Hu

    IPC分类号： H01L29/78

    CPC分类号： H01L29/66712 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7809 ,  H01L29/7816

    摘要： A LDMOS transistor having a channel region located between an outer boundary of an n-type region and an inner boundary of a p-body region. A width of the LDMOS channel region is less than 80% of a distance between an outer boundary of an n+-type region and the inner boundary of a p-body region. Also, a method for making a LDMOS transistor where the n-type dopants are implanted at an angle that is greater than an angle used to implant the p-type dopants. Furthermore, a VDMOS having first and second channel regions located between an inner boundary of a first and second p-body region and an outer boundary of an n-type region of the first and second p-body regions. The width of the first and second channel regions of the VDMOS is less than 80% of a distance between the inner boundary of the first and second p-body regions and an outer boundary of an n+-type region of the first and second p-body regions. Moreover, a method for making a VDMOS transistor where the n-type dopants are implanted at an angle that is greater than an angle used to implant the p-type dopants.

    摘要翻译： 一种LDMOS晶体管，其具有位于n型区域的外边界和p体区域的内边界之间的沟道区域。 LDMOS通道区域的宽度小于n +型区域的外边界与p体区域的内边界之间的距离的80％。 此外，制造LDMOS晶体管的方法，其中n型掺杂剂以大于用于注入p型掺杂剂的角度的角度注入。 此外，VDMOS具有位于第一和第二p体区域的内边界和第一和第二p体区域的n型区域的外边界之间的第一和第二沟道区域。 VDMOS的第一和第二沟道区域的宽度小于第一和第二p体区域的内边界与第一和第二p体区域的n +型区域的外边界之间的距离的80％ 身体区域。 此外，制造VDMOS晶体管的方法，其中n型掺杂剂以大于用于注入p型掺杂剂的角度的角度注入。