公开(公告)号：US20110241130A1

公开(公告)日：2011-10-06

申请号：US12753372

申请日：2010-04-02

Applicant: Bor-Wen CHAN ,  Hsueh Wen Tsau

Inventor： Bor-Wen CHAN ,  Hsueh Wen Tsau

IPC: H01L29/78 ,  H01L23/532 ,  H01L21/768 ,  H01L21/3205

CPC classification number: H01L29/401 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/2855 ,  H01L21/67207 ,  H01L21/76846 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a blocking structure between a metal layer and at least one underlying layer. The blocking structure has a first layer configured for preventing diffusion of metal from the metal layer into the at least one underlying layer, and a second layer configured for enhancing electrical performance of the semiconductor device.

Abstract translation: 半导体器件包括在金属层和至少一个下层之间的阻挡结构。 阻挡结构具有被配置为防止金属从金属层扩散到至少一个下层中的第一层，以及被配置用于增强半导体器件的电性能的第二层。

公开(公告)号：US08093117B2

公开(公告)日：2012-01-10

申请号：US12687714

申请日：2010-01-14

Applicant: Hsueh Wen Tsau ,  Kuang-Yuan Hsu ,  Bor-Wen Chan

Inventor： Hsueh Wen Tsau ,  Kuang-Yuan Hsu ,  Bor-Wen Chan

IPC: H01L21/338

CPC classification number: H01L21/28088 ,  H01L21/0228 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a substrate. A dummy gate is formed over the substrate. A dielectric material is formed around the dummy gate. The dummy gate is then removed to form an opening in the dielectric material. Thereafter, a work function metal layer is formed to partially fill the opening. The remainder of the opening is then filled with a conductive layer using one of a polysilicon substitute method and a spin coating method.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括提供基板。 在基板上形成虚拟栅极。 在虚拟栅极周围形成电介质材料。 然后去除伪栅极以在电介质材料中形成开口。 此后，形成功函数金属层以部分地填充开口。 然后使用多晶硅替代方法和旋涂方法之一用导电层填充开口的剩余部分。

公开(公告)号：US08564072B2

公开(公告)日：2013-10-22

申请号：US12753372

申请日：2010-04-02

Applicant: Bor-Wen Chan ,  Hsueh Wen Tsau

Inventor： Bor-Wen Chan ,  Hsueh Wen Tsau

IPC: H01L21/70

CPC classification number: H01L29/401 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/2855 ,  H01L21/67207 ,  H01L21/76846 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a blocking structure between a metal layer and at least one underlying layer. The blocking structure has a first layer configured for preventing diffusion of metal from the metal layer into the at least one underlying layer, and a second layer configured for enhancing electrical performance of the semiconductor device.

Abstract translation: 半导体器件包括在金属层和至少一个下层之间的阻挡结构。 阻挡结构具有被配置为防止金属从金属层扩散到至少一个下层中的第一层，以及被配置用于增强半导体器件的电性能的第二层。

公开(公告)号：US20110171820A1

公开(公告)日：2011-07-14

申请号：US12687714

申请日：2010-01-14

Applicant: Hsueh Wen Tsau ,  Kuang-Yuan Hsu ,  Bor-Wen Chan

Inventor： Hsueh Wen Tsau ,  Kuang-Yuan Hsu ,  Bor-Wen Chan

IPC: H01L21/28

CPC classification number: H01L21/28088 ,  H01L21/0228 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a substrate. A dummy gate is formed over the substrate. A dielectric material is formed around the dummy gate. The dummy gate is then removed to form an opening in the dielectric material. Thereafter, a work function metal layer is formed to partially fill the opening. The remainder of the opening is then filled with a conductive layer using one of a polysilicon substitute method and a spin coating method.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括提供基板。 在基板上形成虚拟栅极。 在虚拟栅极周围形成电介质材料。 然后去除伪栅极以在电介质材料中形成开口。 此后，形成功函数金属层以部分地填充开口。 然后使用多晶硅替代方法和旋涂方法之一用导电层填充开口的剩余部分。

公开(公告)号：US20110151655A1

公开(公告)日：2011-06-23

申请号：US12641560

申请日：2009-12-18

Applicant: Bor-Wen Chan ,  Hsueh Wen Tsau ,  Kuang-Yuan Hsu

Inventor： Bor-Wen Chan ,  Hsueh Wen Tsau ,  Kuang-Yuan Hsu

IPC: H01L21/28

CPC classification number: H01L29/7848 ,  H01L21/28079 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/495 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7834

Abstract: The present disclosure provides various methods of fabricating a semiconductor device. A method of fabricating a semiconductor device includes providing a semiconductor substrate and forming a gate structure over the substrate. The gate structure includes a first spacer and a second spacer formed apart from the first spacer. The gate structure also includes a dummy gate formed between the first and second spacers. The method also includes removing a portion of the dummy gate from the gate structure thereby forming a partial trench. Additionally, the method includes removing a portion of the first spacer and a portion of the second spacer adjacent the partial trench thereby forming a widened portion of the partial trench. In addition, the method includes removing a remaining portion of the dummy gate from the gate structure thereby forming a full trench. A high k film and a metal gate are formed in the full trench.

Abstract translation: 本公开提供制造半导体器件的各种方法。 制造半导体器件的方法包括提供半导体衬底并在衬底上形成栅极结构。 栅极结构包括第一间隔物和与第一间隔物分开形成的第二间隔物。 栅极结构还包括形成在第一和第二间隔物之间​​的虚拟栅极。 该方法还包括从栅极结构中去除伪栅极的一部分，从而形成部分沟槽。 此外，该方法包括移除第一间隔物的一部分和邻近部分沟槽的第二间隔物的一部分，从而形成部分沟槽的加宽部分。 此外，该方法包括从栅极结构中去除伪栅极的剩余部分，从而形成全沟槽。 在整个沟槽中形成高k膜和金属栅极。

公开(公告)号：US08357603B2

公开(公告)日：2013-01-22

申请号：US12641560

申请日：2009-12-18

Applicant: Bor-Wen Chan ,  Hsueh Wen Tsau ,  Kuang-Yuan Hsu

Inventor： Bor-Wen Chan ,  Hsueh Wen Tsau ,  Kuang-Yuan Hsu

IPC: H01L21/4763

CPC classification number: H01L29/7848 ,  H01L21/28079 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/495 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7834

Abstract: The present disclosure provides various methods of fabricating a semiconductor device. A method of fabricating a semiconductor device includes providing a semiconductor substrate and forming a gate structure over the substrate. The gate structure includes a first spacer and a second spacer formed apart from the first spacer. The gate structure also includes a dummy gate formed between the first and second spacers. The method also includes removing a portion of the dummy gate from the gate structure thereby forming a partial trench. Additionally, the method includes removing a portion of the first spacer and a portion of the second spacer adjacent the partial trench thereby forming a widened portion of the partial trench. In addition, the method includes removing a remaining portion of the dummy gate from the gate structure thereby forming a full trench. A high k film and a metal gate are formed in the full trench.

Abstract translation: 本公开提供制造半导体器件的各种方法。 制造半导体器件的方法包括提供半导体衬底并在衬底上形成栅极结构。 栅极结构包括第一间隔物和与第一间隔物分开形成的第二间隔物。 栅极结构还包括形成在第一和第二间隔物之间​​的虚拟栅极。 该方法还包括从栅极结构中去除伪栅极的一部分，从而形成部分沟槽。 此外，该方法包括移除第一间隔物的一部分和邻近部分沟槽的第二间隔物的一部分，从而形成部分沟槽的加宽部分。 此外，该方法包括从栅极结构中去除伪栅极的剩余部分，从而形成全沟槽。 在整个沟槽中形成高k膜和金属栅极。

公开(公告)号：US09105653B2

公开(公告)日：2015-08-11

申请号：US12982451

申请日：2010-12-30

Applicant: Hsueh Wen Tsau

Inventor： Hsueh Wen Tsau

IPC: H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/28568 ,  H01L21/31116 ,  H01L21/3212 ,  H01L21/823842 ,  H01L21/82385

Abstract: An exemplary method for fabricating a metal gate electrode includes providing a substrate having thereon a dielectric layer and a trench in the dielectric layer; depositing a work-function metal layer over the dielectric layer and into the trench; depositing a sacrificial layer over the work-function metal layer to fill the first trench; performing a chemical mechanical polishing to remove the work-function metal layer outside the trench; removing the sacrificial layer in the trench; and depositing a signal metal layer to fill the trench.

Abstract translation: 一种用于制造金属栅电极的示例性方法包括在介电层中提供其上具有电介质层和沟槽的衬底; 在电介质层上沉积工作功能金属层并进入沟槽; 在所述功函数金属层上沉积牺牲层以填充所述第一沟槽; 进行化学机械抛光以除去沟槽外的功函数金属层; 去除沟槽中的牺牲层; 以及沉积信号金属层以填充沟槽。

公开(公告)号：US09755039B2

公开(公告)日：2017-09-05

申请号：US13192718

申请日：2011-07-28

Applicant: Hsueh Wen Tsau

Inventor： Hsueh Wen Tsau

IPC: H01L21/70 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/51

CPC classification number: H01L29/4983 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7833

Abstract: A semiconductor device includes a substrate, a gate dielectric layer on the substrate, and a gate electrode stack on the gate dielectric layer. The gate electrode stack includes a metal filling line, a wetting layer, a metal diffusion blocking layer, and a work function layer. The wetting layer is in contact with a sidewall and a bottom surface of the metal filling line. The metal diffusion blocking layer is in contact with the wetting layer and covers the sidewall and the bottom surface of the metal filling line with the wetting layer therebetween. The work function layer covers the sidewall and the bottom surface of the metal filling line with the wetting layer and the metal diffusion blocking layer therebetween.

公开(公告)号：US20140027822A1

公开(公告)日：2014-01-30

申请号：US13557592

申请日：2012-07-25

Applicant: Li-Lin Su ,  Ching-Hua Hsieh ,  Huang-Ming Chen ,  Hsueh Wen Tsau

Inventor： Li-Lin Su ,  Ching-Hua Hsieh ,  Huang-Ming Chen ,  Hsueh Wen Tsau

IPC: H01L23/485 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L23/535 ,  H01L21/28035 ,  H01L21/28088 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76879 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device includes a conductive layer including a bottom portion, and a sidewall portion over the bottom portion, wherein the sidewall portion is connected to an end of the bottom portion. An aluminum-containing layer overlaps the bottom portion of the conductive layer, wherein a top surface of the aluminum-containing layer is substantially level with a top edge of the sidewall portion of the conductive layer. An aluminum oxide layer is overlying the aluminum-containing layer. A copper-containing region is over the aluminum oxide layer, and is spaced apart from the aluminum-containing layer by the aluminum oxide layer. The copper-containing region is electrically coupled to the aluminum-containing layer through the top edge of the sidewall portion of the conductive layer.

Abstract translation: 一种器件包括一个包括一个底部的导电层和一个位于底部上的侧壁部分，其中侧壁部分连接到底部的一端。 含铝层与导电层的底部重叠，其中含铝层的顶表面与导电层的侧壁部分的顶部边缘基本平齐。 铝氧化物层覆盖含铝层。 含铜区域位于氧化铝层的上方，并且通过氧化铝层与含铝层隔开。 含铜区域通过导电层的侧壁部分的顶边缘电耦合到含铝层。

公开(公告)号：US09136206B2

公开(公告)日：2015-09-15

申请号：US13557592

申请日：2012-07-25

Applicant: Li-Lin Su ,  Ching-Hua Hsieh ,  Huang-Ming Chen ,  Hsueh Wen Tsau

Inventor： Li-Lin Su ,  Ching-Hua Hsieh ,  Huang-Ming Chen ,  Hsueh Wen Tsau

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/485 ,  H01L29/49 ,  H01L23/522 ,  H01L23/532 ,  H01L29/66

CPC classification number: H01L23/535 ,  H01L21/28035 ,  H01L21/28088 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76879 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device includes a conductive layer including a bottom portion, and a sidewall portion over the bottom portion, wherein the sidewall portion is connected to an end of the bottom portion. An aluminum-containing layer overlaps the bottom portion of the conductive layer, wherein a top surface of the aluminum-containing layer is substantially level with a top edge of the sidewall portion of the conductive layer. An aluminum oxide layer is overlying the aluminum-containing layer. A copper-containing region is over the aluminum oxide layer, and is spaced apart from the aluminum-containing layer by the aluminum oxide layer. The copper-containing region is electrically coupled to the aluminum-containing layer through the top edge of the sidewall portion of the conductive layer.

Abstract translation: 一种器件包括一个包括一个底部的导电层和一个位于底部上的侧壁部分，其中侧壁部分连接到底部的一端。 含铝层与导电层的底部重叠，其中含铝层的顶表面与导电层的侧壁部分的顶部边缘基本平齐。 铝氧化物层覆盖含铝层。 含铜区域位于氧化铝层的上方，并且通过氧化铝层与含铝层隔开。 含铜区域通过导电层的侧壁部分的顶边缘电耦合到含铝层。