公开(公告)号：US09442737B2

公开(公告)日：2016-09-13

申请号：US13524833

申请日：2012-06-15

申请人： Khary J. Alexander ,  Brenton F. Belmar ,  Christian Jacobi ,  Randall W. Philley ,  Anthony Saporito ,  Timothy J. Slegel

发明人： Khary J. Alexander ,  Brenton F. Belmar ,  Christian Jacobi ,  Randall W. Philley ,  Anthony Saporito ,  Timothy J. Slegel

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/52 ,  G06F9/46

CPC分类号： G06F9/3861 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/38 ,  G06F9/3857 ,  G06F9/466 ,  G06F9/467 ,  G06F9/52 ,  G06F9/524

摘要： Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors.

公开(公告)号：US20130339684A1

公开(公告)日：2013-12-19

申请号：US13524833

申请日：2012-06-15

申请人： Khary J. Alexander ,  Brenton F. Belmar ,  Christian Jacobi ,  Randall W. Philley ,  Anthony Saporito ,  Timothy J. Slegel

发明人： Khary J. Alexander ,  Brenton F. Belmar ,  Christian Jacobi ,  Randall W. Philley ,  Anthony Saporito ,  Timothy J. Slegel

IPC分类号： G06F9/30

CPC分类号： G06F9/3861 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/38 ,  G06F9/3857 ,  G06F9/466 ,  G06F9/467 ,  G06F9/52 ,  G06F9/524

摘要： Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors.

公开(公告)号：US09740549B2

公开(公告)日：2017-08-22

申请号：US13524857

申请日：2012-06-15

申请人： Brenton F. Belmar ,  Christian Jacobi ,  Randall W. Philley ,  Timothy J. Slegel

发明人： Brenton F. Belmar ,  Christian Jacobi ,  Randall W. Philley ,  Timothy J. Slegel

IPC分类号： G06F7/00 ,  G06F17/00 ,  G06F11/07 ,  G06F17/30 ,  G06F9/46 ,  G06F13/24

CPC分类号： G06F11/076 ,  G06F9/466 ,  G06F11/0721 ,  G06F13/24 ,  G06F17/30371

摘要： Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors.

公开(公告)号：US09311101B2

公开(公告)日：2016-04-12

申请号：US13524370

申请日：2012-06-15

申请人： Brenton F. Belmar ,  Mark S. Farrell ,  Christian Jacobi ,  Timothy J. Slegel

发明人： Brenton F. Belmar ,  Mark S. Farrell ,  Christian Jacobi ,  Timothy J. Slegel

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F9/46

CPC分类号： G06F9/3857 ,  G06F9/30 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3859 ,  G06F9/466 ,  G06F9/467

摘要： Embodiments relate to intra-instructional transaction abort handling. An aspect includes using an emulation routine to execute an instruction within a transaction. The instruction includes at least one unit of operation. The transaction effectively delays committing stores to memory until the transaction has completed successfully. After receiving an abort indication, emulation of the instruction is terminated prior to completing the execution of the instruction. The instruction is terminated after the emulation routine completes any previously initiated unit of operation of the instruction.

摘要翻译： 实施例涉及教学内交易中止处理。 一方面包括使用仿真例程来执行事务内的指令。 该指令至少包含一个操作单元。 交易有效地延迟提交存储到内存，直到事务成功完成。 在接收到中止指示之后，在完成执行指令之前终止指令的仿真。 在仿真程序完成任何先前启动的指令的操作单元之后，指令终止。

公开(公告)号：US20130339673A1

公开(公告)日：2013-12-19

申请号：US13524370

申请日：2012-06-15

申请人： Brenton F. Belmar ,  Mark S. Farrell ,  Christian Jacobi ,  Timothy J. Slegel

发明人： Brenton F. Belmar ,  Mark S. Farrell ,  Christian Jacobi ,  Timothy J. Slegel

IPC分类号： G06F9/30

CPC分类号： G06F9/3857 ,  G06F9/30 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3859 ,  G06F9/466 ,  G06F9/467

摘要： Embodiments relate to intra-instructional transaction abort handling. An aspect includes using an emulation routine to execute an instruction within a transaction. The instruction includes at least one unit of operation. The transaction effectively delays committing stores to memory until the transaction has completed successfully. After receiving an abort indication, emulation of the instruction is terminated prior to completing the execution of the instruction. The instruction is terminated after the emulation routine completes any previously initiated unit of operation of the instruction.

公开(公告)号：US09367323B2

公开(公告)日：2016-06-14

申请号：US13524871

申请日：2012-06-15

申请人： Dan F. Greiner ,  Christian Jacobi ,  Randall W. Philley ,  Peter J. Relson ,  Timothy J. Slegel

发明人： Dan F. Greiner ,  Christian Jacobi ,  Randall W. Philley ,  Peter J. Relson ,  Timothy J. Slegel

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F9/46

CPC分类号： G06F9/3861 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/466

摘要： An operation is provided to signal a processor that action is to be taken to facilitate execution of a transaction that has aborted one or more times. The operation is specified within an instruction or is itself an instruction. The instruction is executed based on detecting an abort of the transactions, and includes a field indicating how many times the transaction has aborted. The processor uses this information to determine what action is to be taken.

摘要翻译： 提供了一种操作来向处理器发出信号，该操作将采取行动来促进已经中止一次或多次的事务的执行。 操作在指令中指定或本身是指令。 该指令是基于检测到事务中止而执行的，并且包括指示事务中止多少次的字段。 处理器使用这些信息来确定要采取的行动。

公开(公告)号：US20130339687A1

公开(公告)日：2013-12-19

申请号：US13524871

申请日：2012-06-15

申请人： Dan F. Greiner ,  Christian Jacobi ,  Randall W. Philley ,  Peter J. Relson ,  Timothy J. Slegel

发明人： Dan F. Greiner ,  Christian Jacobi ,  Randall W. Philley ,  Peter J. Relson ,  Timothy J. Slegel

IPC分类号： G06F9/30

CPC分类号： G06F9/3861 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/466

摘要： An operation is provided to signal a processor that action is to be taken to facilitate execution of a transaction that has aborted one or more times. The operation is specified within an instruction or is itself an instruction. The instruction is executed based on detecting an abort of the transactions, and includes a field indicating how many times the transaction has aborted. The processor uses this information to determine what action is to be taken.

公开(公告)号：US09459868B2

公开(公告)日：2016-10-04

申请号：US13421599

申请日：2012-03-15

申请人： Jonathan D. Bradbury ,  Michael K. Gschwind ,  Christian Jacobi ,  Eric M. Schwarz ,  Timothy J. Slegel

发明人： Jonathan D. Bradbury ,  Michael K. Gschwind ,  Christian Jacobi ,  Eric M. Schwarz ,  Timothy J. Slegel

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30043 ,  G06F9/30036 ,  G06F9/3013 ,  G06F9/3824 ,  G06F12/0875 ,  G06F2212/452

摘要： A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary is dynamically determined based on a specified type of boundary and one or more characteristics of the processor executing the instruction, such as cache line size or page size used by the processor.

摘要翻译： 加载到块提供了将可变数量的字节数据加载到寄存器中，同时确保指定的存储器边界未被越过。 边界根据指定类型的边界和执行指令的处理器的一个或多个特性（例如由处理器使用的高速缓存行大小或页面大小）动态地确定。

公开(公告)号：US09436477B2

公开(公告)日：2016-09-06

申请号：US13524855

申请日：2012-06-15

申请人： Dan F. Greiner ,  Christian Jacobi ,  Marcel M. Mitran ,  Timothy J. Slegel

发明人： Dan F. Greiner ,  Christian Jacobi ,  Marcel M. Mitran ,  Timothy J. Slegel

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3861 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/3834 ,  G06F9/3859 ,  G06F9/3863

摘要： A TRANSACTION ABORT instruction is used to abort a transaction that is executing in a computing environment. The TRANSACTION ABORT instruction includes at least one field used to specify a user-defined abort code that indicates the specific reason for aborting the transaction. Based on executing the TRANSACTION ABORT instruction, a condition code is provided that indicates whether re-execution of the transaction is recommended.

公开(公告)号：US09218288B2

公开(公告)日：2015-12-22

申请号：US13524063

申请日：2012-06-15

申请人： Khary J. Alexander ,  Ute Gaertner ,  Jonathan T. Hsieh ,  Christian Jacobi ,  Timothy J. Slegel

发明人： Khary J. Alexander ,  Ute Gaertner ,  Jonathan T. Hsieh ,  Christian Jacobi ,  Timothy J. Slegel

IPC分类号： G06F12/02 ,  G06F12/08 ,  G06F3/06

CPC分类号： G06F12/0808 ,  G06F3/0653 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/0891

摘要： A technique is provided for monitoring a value without repeated storage access. A processing circuit processes an instruction of a program that specifies a memory address of a memory location to be monitored. The processing circuit configures a monitor station for monitoring the memory location. The memory location includes a state descriptor for the program. The processing circuit receives a cross-invalidate request from a memory controller. The cross-invalidate request indicates to the monitor station that content of the memory location has been changed by another processing circuit.

摘要翻译： 提供了一种用于监视值而不重复存储访问的技术。 处理电路处理指定要监视的存储器位置的存储器地址的程序的指令。 处理电路配置用于监视存储器位置的监视站。 存储器位置包括程序的状态描述符。 处理电路从存储器控制器接收到交叉无效请求。 交叉无效请求向监视台指示存储器位置的内容已被另一处理电路改变。