Transmitter with a phase modulator and a phase locked loop
    1.
    发明授权
    Transmitter with a phase modulator and a phase locked loop 有权
    具有相位调制器和锁相环的发射机

    公开(公告)号:US06420940B1

    公开(公告)日:2002-07-16

    申请号:US09622213

    申请日:2000-08-14

    IPC分类号: H04L2712

    摘要: A transmitter has a phase modulator and a phase locked loop that has a relatively high powered voltage controlled oscillator. The phase locked loop has a phase sensitive detector for comparing a phase comparison frequency derived from the voltage controlled oscillator output with a phase modulated intermediate frequency carrier derived from the phase modulator. The phase modulator has a reference frequency source, means for deriving four quadrature phase components of the reference frequency produced by the source and phase selection means controlled by complex modulation means for deriving the phase modulated intermediate frequency carrier by random interpolation between the four quadrature components.

    摘要翻译: 发射机具有相位调制器和锁相环,其具有相对较高的受电压控制的振荡器。 锁相环具有相敏检测器,用于将从压控振荡器输出导出的相位比较频率与从相位调制器导出的相位调制中频载波进行比较。 相位调制器具有参考频率源,用于导出由复数调制装置控制的源极和相位选择装置产生的参考频率的四个正交相位分量的装置,用于通过四个正交分量之间的随机内插导出相位调制的中频载波。

    Semiconductor device comprising a two-stage differential amplifier
    2.
    发明授权
    Semiconductor device comprising a two-stage differential amplifier 失效
    半导体器件包括两级差分放大器

    公开(公告)号:US5389891A

    公开(公告)日:1995-02-14

    申请号:US995452

    申请日:1992-12-21

    申请人: Pascal Philippe

    发明人: Pascal Philippe

    IPC分类号: H03F1/02 H03F1/22 H03F3/45

    摘要: A semiconductor device comprises a two-stage differential amplifier, the amplifier comprising a first differential transistor pair whose transistors are coupled by their source electrodes and each receive an input signal, and a second differential transistor pair whose transistors are coupled by their source electrodes, each of these transistors receive the output of one of the branches of the first differential pair, and each supply an output. In the amplifier each branch of the second differential pair is arranged in series with a branch of the first differential pair so as to form two sub-circuits each including a transistor of the first pair with its load and a transistor of the second pair with its load in a manner such that the two transistors of each sub-circuit share the same current.

    摘要翻译: 半导体器件包括两级差分放大器,该放大器包括第一差分晶体管对,其晶体管由其源电极耦合并且各自接收输入信号;以及第二差分晶体管对,其晶体管由其源电极耦合,每个 这些晶体管接收第一差分对的一个分支的输出,并且每个提供输出。 在放大器中,第二差分对的每个分支与第一差分对的分支串联布置,以便形成两个子电路,每个子电路包括第一对晶体管及其负载,第二对的晶体管与其 以使得每个子电路的两个晶体管共享相同电流的方式加载。

    DIGITAL POLAR RADIO FREQUENCY TRANSMITTING DEVICE WITH A RADIOFREQUENCY REFERENCE OSCILLATOR AND AN INTEGRATED CIRCUIT COMPRISING SUCH DEVICE
    3.
    发明申请
    DIGITAL POLAR RADIO FREQUENCY TRANSMITTING DEVICE WITH A RADIOFREQUENCY REFERENCE OSCILLATOR AND AN INTEGRATED CIRCUIT COMPRISING SUCH DEVICE 有权
    具有无线参考振荡器和包含这种装置的集成电路的数字极性无线电频率发射装置

    公开(公告)号:US20100111227A1

    公开(公告)日:2010-05-06

    申请号:US12441524

    申请日:2007-09-14

    申请人: Pascal Philippe

    发明人: Pascal Philippe

    IPC分类号: H04L27/36 H04L27/20

    摘要: A radiofrequency transmitting device delivers output signals having a chosen radiofrequency from input data split up into complementary phase data and amplitude data. This device includes a radiofrequency reference oscillator for outputting a reference signal having a fixed radiofrequency reference, and a digital phase modulator for synthesizing the chosen radiofrequency from the fixed radiofrequency reference and for phase modulating the reference signal with the phase data, in order to produce an output signal having the chosen radiofrequency.

    摘要翻译: 射频发送装置将具有选择的射频的输出信号从输入数据分离成互补相位数据和振幅数据。 该装置包括用于输出具有固定射频参考的参考信号的射频参考振荡器和用于从固定射频参考合成所选择的射频并且用相位数据相位调制参考信号的数字相位调制器,以产生 输出信号具有选择的射频。

    JITTER REDUCTION CIRCUIT AND FREQUENCY SYNTHESIZER
    4.
    发明申请
    JITTER REDUCTION CIRCUIT AND FREQUENCY SYNTHESIZER 有权
    抖动减少电路和频率合成器

    公开(公告)号:US20090224807A1

    公开(公告)日:2009-09-10

    申请号:US11720313

    申请日:2005-11-10

    申请人: Pascal Philippe

    发明人: Pascal Philippe

    CPC分类号: H03K5/1565

    摘要: The jitter reduction circuit to reduce phase noise in a pulse train, comprises: —a resettable integrator (70) to integrate the pulse train, —a comparator (72) to compare the integrated pulse train with a reference level and to generate a modified pulse train with reduced phase noise, —a crossing time interval detector (94) configured to determine a discrete time interval during which the integrated pulse train crosses the reference level and to reset the integrator between two discrete time intervals determined consecutively.

    摘要翻译: 用于减少脉冲序列中的相位噪声的抖动降低电路包括: - 一个用于对脉冲序列进行积分的可复位积分器(70),比较器(72)将积分脉冲串与参考电平进行比较,并产生修正脉冲 具有降低的相位噪声的训练, - 跨度时间间隔检测器(94),其被配置为确定所述积分脉冲串跨过所述参考电平的离散时间间隔,并且在连续确定的两个离散时间间隔之间复位所述积分器。

    VEHICLE LATCH ASSEMBLY AND METHOD OF DAMPENING SOUND DURING A CLOSING PROCESS OF THE VEHICLE LATCH ASSEMBLY
    6.
    发明申请
    VEHICLE LATCH ASSEMBLY AND METHOD OF DAMPENING SOUND DURING A CLOSING PROCESS OF THE VEHICLE LATCH ASSEMBLY 有权
    车辆闭锁装置的闭合过程中的车辆锁定装置和防振方法

    公开(公告)号:US20150191947A1

    公开(公告)日:2015-07-09

    申请号:US14147197

    申请日:2014-01-03

    IPC分类号: E05C3/12

    摘要: A vehicle latch assembly includes a housing having a frame plate. Also included is a claw disposed within the housing and operatively coupled to the frame plate, the claw configured to rotate between an open latch position and a closed latch position. Further included is a claw buffer disposed within the housing and configured to interact with the claw upon rotation to the closed latch position, the claw buffer including at least one abutment portion configured to engage the claw prior to reaching the closed latch position.

    摘要翻译: 车辆闩锁组件包括具有框架板的壳体。 还包括设置在壳体内并可操作地联接到框架板的爪,该爪构造成在打开的闩锁位置和闭合的闩锁位置之间旋转。 进一步包括爪缓冲器,其设置在壳体内并且被配置为在旋转到闭合的锁定位置时与爪相互作用,爪缓冲器包括构造成在达到闭锁闩锁位置之前接合爪的至少一个邻接部分。

    Integrated oscillator and radio telephone using such an oscillator
    8.
    发明授权
    Integrated oscillator and radio telephone using such an oscillator 失效
    使用这种振荡器的集成振荡器和无线电话

    公开(公告)号:US5937340A

    公开(公告)日:1999-08-10

    申请号:US946483

    申请日:1997-10-07

    摘要: The invention relates to an oscillator OSC intended to provide an output signal having a frequency which is variable as a function of a tuning voltage Vtun. The oscillator OSC includes a passive part having two series-arranged variable capacitances Cs, biased by the tuning voltage Vtun, and connected to a power supply VCC via two inductances Lext, and an active part having a first transistor T1 and a second transistor T2 whose collectors are connected to the output terminals C1 and C2 of the passive part, the base of one transistor being connected to the collector of the other transistor via a coupling capacitor Cfb. According to the invention, the passive part includes two high-pass filters, each being inserted between one of the output terminals S1 or S2 and one of the variable capacitances Cs, which allows a reduction of the active part's sensitivity to low-frequency noise.

    摘要翻译: 本发明涉及一种旨在提供具有作为调谐电压Vtun的函数可变的频率的输出信号的振荡器OSC。 振荡器OSC包括具有由调谐电压Vtun偏置的两个串联布置的可变电容Cs的无源部分,并且经由两个电感Lext连接到电源VCC,以及具有第一晶体管T1和第二晶体管T2的有源部分 集电极连接到无源部分的输出端子C1和C2,一个晶体管的基极通过耦合电容器Cfb连接到另一晶体管的集电极。 根据本发明,无源部分包括两个高通滤波器,每个高通滤波器插入在一个输出端子S1或S2和一个可变电容Cs之间,这允许有源部分对低频噪声的灵敏度降低。

    Integrated circuit having a variable-gain amplifier
    9.
    发明授权
    Integrated circuit having a variable-gain amplifier 失效
    具有可变增益放大器的集成电路

    公开(公告)号:US5323123A

    公开(公告)日:1994-06-21

    申请号:US995099

    申请日:1992-12-21

    申请人: Pascal Philippe

    发明人: Pascal Philippe

    CPC分类号: H03D7/125

    摘要: An integrated circuit includes a variable-gain amplifier having a first transistor with a load arranged as an inverted and controlled by a first signal of a first frequency, and also having a branch comprising a capacitance in series with a transistor which is arranged as a variable resistance and whose impedance is modulated by a second signal of a second frequency. In this circuit the variable-gain amplifier comprises a second transistor with a load arranged as an inverter and disposed in series with the first transistor and its load between this load and a d.c. supply, in such a manner that the two inverter transistors share the same current, the second inverter being controlled by the output of the first inverter, and the impedance modulated by the second signal is coupled to a node between the load of the first inverter transistor and the second inverter transistor in order to modulate the gain of the latter.

    摘要翻译: 集成电路包括可变增益放大器,该可变增益放大器具有第一晶体管,负载被布置为反相并由第一频率的第一信号控制,并且还具有包括与被布置为变量的晶体管串联的电容的分支 电阻并且其阻抗由第二频率的第二信号调制。 在该电路中,可变增益放大器包括第二晶体管,其负载被布置为反相器并且与第一晶体管串联布置,并且其负载在该负载和直流电压之间。 以两个逆变器晶体管共享相同电流的方式供电,第二反相器由第一反相器的输出控制,并且由第二信号调制的阻抗耦合到第一反相器晶体管的负载之间的节点 和第二反相器晶体管,以便调制后者的增益。

    Phase Shifter having parallel RC networks
    10.
    发明授权
    Phase Shifter having parallel RC networks 失效
    移相器具有并联RC网络

    公开(公告)号:US5043654A

    公开(公告)日:1991-08-27

    申请号:US534100

    申请日:1990-06-06

    申请人: Pascal Philippe

    发明人: Pascal Philippe

    IPC分类号: H03H7/18 H03H7/21

    CPC分类号: H03H7/21

    摘要: Phase shifter to which are applied two signals in a phase opposition (v, -v) is constituted by a first series circuit of a resistor and a capacitor (R.sub.1, C.sub.1), and a second series circuit of a resistor and a capacitor (R.sub.2, C.sub.2). So that neither the relative amplitudes nor the relative phases of all the signals used at the outputs (5, 6, 7, 8) are degraded by the impedance of the stages that follow, the phase shifter includes a first network of a resistor and a capacitor connected in parallel (C.sub.3, R.sub.3), and a second network of a resistor and a capacitor connected in parallel (C.sub.4, R.sub.4). Both the four resistors and the four capacitors of the phase shifter are each substantially equal in value.

    摘要翻译: 施加相位相对(v,-v)的两个信号的移相器由电阻器和电容器(R1,C1)的第一串联电路和电阻器和电容器的第二串联电路(R2 ,C2)。 因此,输出(5,6,7,8)中使用的所有信号的相对幅度和相对相位均不会随后续级的阻抗而降低,所以移相器包括电阻器的第一网络和 并联的电容器(C3,R3)和并联的电阻器和电容器(C4,R4)的第二网络。 移相器的四个电阻器和四个电容器的值都基本相等。