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    Method and system for generating reference voltages for signal receivers
    2.
    发明授权
    Method and system for generating reference voltages for signal receivers 有权
    用于产生信号接收机参考电压的方法和系统

    公开(公告)号：US07746959B2

    公开(公告)日：2010-06-29

    申请号：US11433322

    申请日：2006-05-11

    申请人： Brent Keeth ,  Joo S. Choi ,  George E. Pax ,  Ronnie M. Harrison ,  David Ovard ,  Dragos Dimitriu ,  Troy A. Manning ,  Roy E. Greeff ,  Greg King ,  Brian Johnson

    发明人： Brent Keeth ,  Joo S. Choi ,  George E. Pax ,  Ronnie M. Harrison ,  David Ovard ,  Dragos Dimitriu ,  Troy A. Manning ,  Roy E. Greeff ,  Greg King ,  Brian Johnson

    IPC分类号： H04L25/06

    CPC分类号： H04L25/062

    摘要： A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In the calibration mode, the magnitude of the reference voltage is incrementally varied, and a digital signal pattern is coupled to the receiver at each reference voltage. An output of the receiver is analyzed to determine if the receiver can accurately pass the signal pattern at each reference voltage level. A range of reference voltages that allow the receiver to accurately pass the signal pattern is recorded, and a final reference voltage is calculated at the approximate midpoint of the range. This final reference voltage is applied to the receiver during normal operation.

    摘要翻译： 用于产生用于存储器件信号接收器的参考电压的方法和系统以校准模式或正常操作模式工作。 在校准模式下，参考电压的幅度逐渐变化，并且数字信号图案在每个参考电压下耦合到接收器。 分析接收机的输出以确定接收机是否可以在每个参考电压电平下准确地传递信号模式。 记录允许接收器精确地通过信号图案的参考电压范围，并且在该范围的大致中点处计算最终参考电压。 在正常操作期间将该最终参考电压施加到接收器。

    Multi-mode synchronous memory device and methods of operating and testing same
    3.
    发明授权
    Multi-mode synchronous memory device and methods of operating and testing same 失效
    多模同步存储器件及其操作和测试方法相同

    公开(公告)号：US07057967B2

    公开(公告)日：2006-06-06

    申请号：US11001231

    申请日：2004-12-01

    申请人： Brian Johnson ,  Brent Keeth ,  Jeffrey W. Janzen ,  Troy A. Manning ,  Chris G. Martin

    发明人： Brian Johnson ,  Brent Keeth ,  Jeffrey W. Janzen ,  Troy A. Manning ,  Chris G. Martin

    IPC分类号： G11C8/00

    CPC分类号： G11C29/12015 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C29/14

    摘要： A synchronous semiconductor memory device is operable in a normal mode and an alternative mode. The semiconductor device has a command bus for receiving a plurality of synchronously captured input signals, and a plurality of asynchronous input terminals for receiving a plurality of asynchronous input signals. The device further has a clock input for receiving an external clock signal thereon, with the device being specified by the manufacturer to be operated in the normal mode using an external clock signal having a frequency no less than a predetermined minimum frequency. An internal delay locked loop (DLL) clocking circuit is coupled to the clock input terminal and is responsive in normal operating mode to be responsive to the external clock signal to generate at least one internal clock signal. control circuitry in the device is responsive to a predetermined sequence of asynchronous signals applied to the device's asynchronous input terminals to place the device in an alternative mode of operation in which the internal clocking circuit is disabled, such that the device may be operated in the alternative mode using an external clock signal having a frequency less than the predetermined minimum frequency. The alternative mode of operation facilitates testing of the device at a speed less than the minimum frequency specified for the normal mode of operation.

    摘要翻译： 同步半导体存储器件可以在正常模式和替代模式下操作。 半导体器件具有用于接收多个同步捕获的输入信号的命令总线和用于接收多个异步输入信号的多个异步输入端子。 该装置还具有用于在其上接收外部时钟信号的时钟输入，该装置由制造商指定为使用具有不小于预定最小频率的频率的外部时钟信号在正常模式下操作。 内部延迟锁定环（DLL）时钟电路耦合到时钟输入端并且在正常操作模式下响应于外部时钟信号响应以产生至少一个内部时钟信号。 设备中的控制电路响应于施加到设备的异步输入端子的预定的异步信号序列，以将设备置于其中内部时钟电路被禁用的替代操作模式，使得该设备可以以替代方式操作 模式使用具有小于预定最小频率的频率的外部时钟信号。 替代的操作模式便于以低于为正常操作模式指定的最小频率的速度测试设备。

    Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device
    5.
    发明授权
    Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device 有权
    用于确定实际写入延迟并准确地将数据捕获的开始与数据到达存储器件的方法和装置

    公开(公告)号：US06697926B2

    公开(公告)日：2004-02-24

    申请号：US09874289

    申请日：2001-06-06

    申请人： Brian Johnson ,  Brent Keeth ,  Troy A. Manning

    发明人： Brian Johnson ,  Brent Keeth ,  Troy A. Manning

    IPC分类号： G06F1200

    CPC分类号： G11C29/028 ,  G06F13/1694 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1093 ,  G11C11/401 ,  G11C29/50012 ,  G11C2207/2254

    摘要： A method and apparatus for accurately determining the actual arrival of data at a memory device relative to the write clock to accurately align the start of data capture and the arrival of the data at the memory device is disclosed. The actual time of arrival of data at the inputs to a memory device is determined by sending back-to-back write commands along with a predetermined data pattern to the memory device. The data pattern is stored in a register and any difference between the predicted arrival time of the data and the actual arrival time of the data is determined by logic circuitry. Any determined difference can then be compensated for by delaying the start of the capture of the data at the memory device, thereby accurately aligning the start of the data capture and the arrival of the data at the memory device.

    摘要翻译： 公开了一种用于准确地确定数据在存储器件相对于写入时钟的实际到达以精确对准数据捕获的开始和数据到存储器件的方法和装置。 将数据到输入到存储器件的实际时间通过与存储器件一起发送背靠背写入命令以及预定数据模式来确定。 数据模式存储在寄存器中，数据的预计到达时间与数据的实际到达时间之间的任何差异由逻辑电路确定。 然后可以通过延迟在存储器件处捕获数据的开始来补偿任何确定的差异，从而将数据捕获的开始和数据的到达准确地对准存储器件。