公开(公告)号：US08461869B1

公开(公告)日：2013-06-11

申请号：US13214147

申请日：2011-08-19

申请人： Irfan Rahim ,  Andy L. Lee ,  Bruce B. Pedersen ,  Jeffrey T. Watt ,  Mao Du ,  Richard G. Cliff

发明人： Irfan Rahim ,  Andy L. Lee ,  Bruce B. Pedersen ,  Jeffrey T. Watt ,  Mao Du ,  Richard G. Cliff

IPC分类号： H03K19/003

CPC分类号： H03K19/003 ,  H03K19/17784

摘要： An apparatus includes a temperature sensor, a voltage regulator, and a field programmable gate array (FPGA). The temperature sensor and the voltage regulator are adapted, respectively, to provide a temperature signal, and to provide at least one output voltage. The FPGA includes at least one circuit adapted to receive the at least one output voltage of the voltage regulator, and a set of monitor circuits adapted to provide indications of process and temperature for the at least one circuit. The FPGA further includes a controller adapted to derive a body-bias signal and a voltage-level signal from the temperature signal, from the indications of process and temperature for the at least one circuit, and from the at least one output voltage of the voltage regulator. The controller is further adapted to provide the body-bias signal to at least one transistor in the at least one circuit, and to provide the voltage-level signal to the voltage regulator.

摘要翻译： 一种装置包括温度传感器，电压调节器和现场可编程门阵列（FPGA）。 温度传感器和电压调节器分别适于提供温度信号，并提供至少一个输出电压。 FPGA包括适于接收电压调节器的至少一个输出电压的至少一个电路，以及适于提供至少一个电路的过程和温度指示的一组监视器电路。 FPGA还包括控制器，其适于从温度信号，从至少一个电路的处理和温度指示以及电压的至少一个输出电压导出体偏置信号和电压电平信号 调节器 所述控制器还适于将所述体偏置信号提供给所述至少一个电路中的至少一个晶体管，并且向所述电压调节器提供所述电压电平信号。

公开(公告)号：US20130002287A1

公开(公告)日：2013-01-03

申请号：US13174599

申请日：2011-06-30

申请人： Bruce B. Pedersen ,  Irfan Rahim

发明人： Bruce B. Pedersen ,  Irfan Rahim

IPC分类号： H03K19/003 ,  H01L35/00 ,  H01L41/00 ,  H01L25/00

CPC分类号： H03K19/17752 ,  H03K19/003

摘要： In an exemplary embodiment, an apparatus includes a first set of circuit elements and a second set of circuit elements. The first set of circuit elements is used in a first configuration of the apparatus, and the second set of circuit elements is used in a second configuration of the apparatus. The first configuration of the apparatus is switched to the second configuration of the apparatus in order to improve reliability of the apparatus.

摘要翻译： 在示例性实施例中，装置包括第一组电路元件和第二组电路元件。 第一组电路元件用于装置的第一配置，并且第二组电路元件用于装置的第二配置。 该设备的第一配置被切换到设备的第二配置，以便提高设备的可靠性。

公开(公告)号：US09455715B2

公开(公告)日：2016-09-27

申请号：US13174599

申请日：2011-06-30

申请人： Bruce B. Pedersen ,  Irfan Rahim

发明人： Bruce B. Pedersen ,  Irfan Rahim

IPC分类号： H03K19/177 ,  H03K19/00 ,  H03K19/003

CPC分类号： H03K19/17752 ,  H03K19/003

摘要： In an exemplary embodiment, an apparatus includes a first set of circuit elements and a second set of circuit elements. The first set of circuit elements is used in a first configuration of the apparatus, and the second set of circuit elements is used in a second configuration of the apparatus. The first configuration of the apparatus is switched to the second configuration of the apparatus in order to improve reliability of the apparatus.

摘要翻译： 在示例性实施例中，装置包括第一组电路元件和第二组电路元件。 第一组电路元件用于装置的第一配置，并且第二组电路元件用于装置的第二配置。 该设备的第一配置被切换到设备的第二配置，以便提高设备的可靠性。

公开(公告)号：US07352610B1

公开(公告)日：2008-04-01

申请号：US11295815

申请日：2005-12-06

申请人： Bruce B. Pedersen ,  Irfan Rahim ,  Jeffrey T Watt

发明人： Bruce B. Pedersen ,  Irfan Rahim ,  Jeffrey T Watt

IPC分类号： G11C11/00

CPC分类号： G11C11/4125

摘要： Memory elements are provided that are immune to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements have nonlinear high-impedance two-terminal elements that restrict the flow of discharge currents during a particle strike. By lengthening the switching speed of the memory elements, the presence of the nonlinear high-impedance two-terminal elements prevents the states of the memory elements from flipping during discharge transients. The nonlinear high-impedance two-terminal elements may be formed from polysilicon p-n junction diodes, Schottky diodes, and other semiconductor structures. Data loading circuitry is provided to ensure that memory element arrays using the nonlinear high-impedance two-terminal elements can be loaded rapidly.

摘要翻译： 提供存储元件，当受到高能原子粒子撞击时，可以免受软错误不安事件的影响。 存储器元件具有非线性高阻抗二端元件，其限制了粒子撞击期间放电电流的流动。 通过延长存储元件的切换速度，非线性高阻抗二端元件的存在防止存储元件的状态在放电瞬变期间翻转。 非线性高阻抗二端元件可以由多晶硅p-n结二极管，肖特基二极管和其它半导体结构形成。 提供数据加载电路以确保使用非线性高阻抗二端元件的存储元件阵列可以快速加载。

公开(公告)号：US09438418B1

公开(公告)日：2016-09-06

申请号：US13102673

申请日：2011-05-06

申请人： Bruce B. Pedersen ,  Ninh D. Ngo

发明人： Bruce B. Pedersen ,  Ninh D. Ngo

IPC分类号： H04L9/08 ,  H04L29/06 ,  H04L9/14

CPC分类号： H04L9/0861 ,  G09C1/00 ,  H04L9/14 ,  H04L9/3239 ,  H04L63/0478 ,  H04L63/06

摘要： Systems and methods relating to generating a key that is difficult to clone are described. The methods include receiving a programmable logic device (PLD) with a first key and applying a one-way hash function to a second key or the first key and the second key to create a third key. The application of the one-way hash function is performed using one or more components hardwired into the PLD. The methods further include storing the third key in the PLD only after using the one or more components to apply the one-way hash function.

摘要翻译： 描述与生成难以克隆的密钥有关的系统和方法。 所述方法包括用第一密钥接收可编程逻辑器件（PLD），并将单向散列函数应用于第二密钥或第一密钥和第二密钥以创建第三密钥。 单向散列函数的应用使用硬连线到PLD中的一个或多个组件来执行。 所述方法还包括仅在使用所述一个或多个组件来应用所述单向散列函数之后将所述第三密钥存储在所述PLD中。

公开(公告)号：US09331848B1

公开(公告)日：2016-05-03

申请号：US13098315

申请日：2011-04-29

申请人： Bruce B. Pedersen

发明人： Bruce B. Pedersen

IPC分类号： H04L9/00 ,  H04L9/06

CPC分类号： H04L9/0631 ,  G09C1/00 ,  H04L9/003 ,  H04L9/0637 ,  H04L2209/04

摘要： Circuits, methods, and systems are provided for securing an integrated circuit device against Differential Power Analysis (DPA) attacks. Plaintext (e.g., configuration data for a programmable device) may be encrypted in an encryption system using a cryptographic algorithm. Ciphertext may be decrypted in a decryption system using the cryptographic algorithm. The encryption and/or decryption systems may obfuscate the plaintext, the ciphertext, and/or the substitution tables used by the cryptographic algorithm. The encryption and/or decryption systems may also generate cryptographic key schedules by using different keys for encrypting/decrypting different blocks and/or by expanding round keys between encryption/decryption blocks. These techniques may help mitigate or altogether eliminate the vulnerability of cryptographic elements revealing power consumption information to learn the value of secret information, e.g., through DPA.

摘要翻译： 提供了电路，方法和系统，用于保护集成电路设备免受差分功耗分析（DPA）攻击。 可以使用加密算法在加密系统中加密明文（例如，可编程设备的配置数据）。 可以在使用密码算法的解密系统中解密密文。 加密和/或解密系统可能会混淆密码算法使用的明文，密文和/或替换表。 加密和/或解密系统还可以通过使用用于加密/解密不同块的不同密钥和/或通过在加密/解密块之间扩展循环密钥来生成加密密钥调度。 这些技术可以有助于减轻或完全消除揭示功耗信息的密码元件的漏洞，以便学习秘密信息的价值，例如通过DPA。

公开(公告)号：US08719957B2

公开(公告)日：2014-05-06

申请号：US13098074

申请日：2011-04-29

申请人： Bruce B. Pedersen

发明人： Bruce B. Pedersen

IPC分类号： G08B21/00 ,  G06F12/14

CPC分类号： G06F21/86 ,  G06F21/76 ,  H03K19/17768

摘要： Systems and methods are disclosed for preventing tampering of a programmable integrated circuit device. Generally, programmable devices, such as FPGAs, have two stages of operation; a configuration stage and a user mode stage. To prevent tampering and/or reverse engineering of a programmable device, various anti-tampering techniques may be employed during either stage of operation to disable the device and/or erase sensitive information stored on the device once tampering is suspected. One type of tampering involves bombarding the device with a number of false configuration attempts in order to decipher encrypted data. By utilizing a dirty bit and a sticky error counter, the device can keep track of the number of failed configuration attempts that have occurred and initiate anti-tampering operations when tampering is suspected while the device is still in the configuration stage of operation.

摘要翻译： 公开了用于防止可编程集成电路器件的篡改的系统和方法。 通常，可编程器件（如FPGA）具有两个操作阶段; 配置阶段和用户模式阶段。 为了防止可编程设备的篡改和/或反向工程，可以在任何操作阶段中采用各种防篡改技术，以在怀疑篡改之后禁用设备和/或擦除存储在设备上的敏感信息。 一种类型的篡改涉及用许多虚假配置尝试来轰炸设备以便解密加密的数据。 通过使用脏位和粘性错误计数器，设备可以跟踪发生的失败配置尝试次数，并在设备处于配置阶段怀疑篡改时启动防篡改操作。

公开(公告)号：US08482965B2

公开(公告)日：2013-07-09

申请号：US13411436

申请日：2012-03-02

申请人： Bruce B. Pedersen

发明人： Bruce B. Pedersen

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  G11C7/20 ,  G11C11/4125 ,  H03K19/00392 ,  H03K19/177 ,  H03K19/1776 ,  H03K19/17764

摘要： Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors including two address transistors and four transistor pairs that are interconnected to form a bistable element. Clear lines such as true and complement clear lines may be routed to positive power supply terminals and ground power supply terminals associated with certain transistor pairs. During clear operations, some or all of the transistor pairs can be selectively depowered using the clear lines. This facilitates clear operations in which logic zero values are driven through the address transistors and reduces cross-bar current surges.

摘要翻译： 提供了存储元件，当受到高能原子粒子撞击时，表现出对软错误失调事件的抵抗力。 存储元件可以各自具有十个晶体管，其包括互连以形成双稳态元件的两个地址晶体管和四个晶体管对。 诸如真实和补充清除线之类的清除线可以被路由到与某些晶体管对相关联的正电源端子和接地电源端子。 在清除操作期间，可以使用清除线选择性地削弱部分或全部晶体管对。 这有助于明确的操作，其中逻辑零值通过地址晶体管驱动并且减小交叉电流浪涌。

公开(公告)号：US20130007679A1

公开(公告)日：2013-01-03

申请号：US13369226

申请日：2012-02-08

申请人： David W. Mendel ,  Gary Lai ,  Lu Zhou ,  Bruce B. Pedersen

发明人： David W. Mendel ,  Gary Lai ,  Lu Zhou ,  Bruce B. Pedersen

IPC分类号： G06F17/50

CPC分类号： G06F17/5054 ,  G06F11/1008 ,  H03K19/17756 ,  H03K19/17776

摘要： A programmable logic device includes logic blocks such as a logic array blocks (LAB) that can be configured as a random access memory (RAM) or as a lookup table (LUT). A mode flag is provided to indicate the mode of operation of configuration logic such as a configuration RAM (CRAM) used during partial reconfiguration of a logic block. An enable read flag is provided to indicate if values stored in the configuration logic are to be read out or a known state is to be read out during a data verification process. Thus, exclusion and inclusion of portions of a region of configuration logic from data verification and correction processes allow a region of configuration logic to store both a design state and a user defined state. Moreover, the region of configuration logic may be dynamically reconfigured from one state to another without causing verification errors.

摘要翻译： 可编程逻辑器件包括诸如可被配置为随机存取存储器（RAM）或查找表（LUT）的逻辑阵列块（LAB）的逻辑块。 提供模式标志以指示诸如在逻辑块的部分重新配置期间使用的配置RAM（CRAM）的配置逻辑的操作模式。 提供使能读取标志以指示在数据验证处理期间是否读出存储在配置逻辑中的值或者是否读出已知状态。 因此，排除和包含来自数据验证和校正处理的配置逻辑区域的部分允许配置逻辑的区域存储设计状态和用户定义的状态。 此外，配置逻辑的区域可以从一个状态被动态地重新配置而不引起验证错误。

公开(公告)号：US20120275077A1

公开(公告)日：2012-11-01

申请号：US13097313

申请日：2011-04-29

申请人： Bruce B. Pedersen ,  Dirk A. Reese

发明人： Bruce B. Pedersen ,  Dirk A. Reese

IPC分类号： H02H9/04

CPC分类号： G11C7/24 ,  H03K19/17768

摘要： Systems and methods are disclosed for securing a programmable integrated circuit device against an over-voltage attack. Generally, programmable devices, such as FPGAs, contain volatile memory registers that may store sensitive information. To prevent tampering and/or reverse engineering of such a programmable device, an over-voltage detection circuit may be employed to disable the device and/or erase the sensitive information stored on the device when an over-voltage attack is suspected. In particular, once the over-voltage detection circuit detects that the voltage applied to the programmable device exceeds a trigger voltage, it may cause logic circuitry to erase the sensitive information stored on the device. Desirably, the over-voltage detection circuit includes components arranged in such a way as to render current consumption negligible when the voltage applied to the programmable device, e.g., by a battery, remains below the trigger voltage.

摘要翻译： 公开了用于保护可编程集成电路装置免受过电压攻击的系统和方法。 通常，可编程器件（如FPGA）包含可能存储敏感信息的易失性存储器寄存器。 为了防止这种可编程设备的篡改和/或逆向工程，当怀疑有过电压攻击时，可以采用过电压检测电路来禁止该设备和/或擦除存储在设备上的敏感信息。 特别地，一旦过电压检测电路检测到施加到可编程器件的电压超过触发电压，则可能导致逻辑电路擦除存储在器件上的敏感信息。 期望地，过电压检测电路包括以下方式布置的组件，即当例如通过电池施加到可编程器件的电压保持低于触发电压时，电流消耗可以忽略不计。