公开(公告)号：US08461869B1

公开(公告)日：2013-06-11

申请号：US13214147

申请日：2011-08-19

申请人： Irfan Rahim ,  Andy L. Lee ,  Bruce B. Pedersen ,  Jeffrey T. Watt ,  Mao Du ,  Richard G. Cliff

发明人： Irfan Rahim ,  Andy L. Lee ,  Bruce B. Pedersen ,  Jeffrey T. Watt ,  Mao Du ,  Richard G. Cliff

IPC分类号： H03K19/003

CPC分类号： H03K19/003 ,  H03K19/17784

摘要： An apparatus includes a temperature sensor, a voltage regulator, and a field programmable gate array (FPGA). The temperature sensor and the voltage regulator are adapted, respectively, to provide a temperature signal, and to provide at least one output voltage. The FPGA includes at least one circuit adapted to receive the at least one output voltage of the voltage regulator, and a set of monitor circuits adapted to provide indications of process and temperature for the at least one circuit. The FPGA further includes a controller adapted to derive a body-bias signal and a voltage-level signal from the temperature signal, from the indications of process and temperature for the at least one circuit, and from the at least one output voltage of the voltage regulator. The controller is further adapted to provide the body-bias signal to at least one transistor in the at least one circuit, and to provide the voltage-level signal to the voltage regulator.

摘要翻译： 一种装置包括温度传感器，电压调节器和现场可编程门阵列（FPGA）。 温度传感器和电压调节器分别适于提供温度信号，并提供至少一个输出电压。 FPGA包括适于接收电压调节器的至少一个输出电压的至少一个电路，以及适于提供至少一个电路的过程和温度指示的一组监视器电路。 FPGA还包括控制器，其适于从温度信号，从至少一个电路的处理和温度指示以及电压的至少一个输出电压导出体偏置信号和电压电平信号 调节器 所述控制器还适于将所述体偏置信号提供给所述至少一个电路中的至少一个晶体管，并且向所述电压调节器提供所述电压电平信号。

公开(公告)号：US20130002287A1

公开(公告)日：2013-01-03

申请号：US13174599

申请日：2011-06-30

申请人： Bruce B. Pedersen ,  Irfan Rahim

发明人： Bruce B. Pedersen ,  Irfan Rahim

IPC分类号： H03K19/003 ,  H01L35/00 ,  H01L41/00 ,  H01L25/00

CPC分类号： H03K19/17752 ,  H03K19/003

摘要： In an exemplary embodiment, an apparatus includes a first set of circuit elements and a second set of circuit elements. The first set of circuit elements is used in a first configuration of the apparatus, and the second set of circuit elements is used in a second configuration of the apparatus. The first configuration of the apparatus is switched to the second configuration of the apparatus in order to improve reliability of the apparatus.

摘要翻译： 在示例性实施例中，装置包括第一组电路元件和第二组电路元件。 第一组电路元件用于装置的第一配置，并且第二组电路元件用于装置的第二配置。 该设备的第一配置被切换到设备的第二配置，以便提高设备的可靠性。

公开(公告)号：US09455715B2

公开(公告)日：2016-09-27

申请号：US13174599

申请日：2011-06-30

申请人： Bruce B. Pedersen ,  Irfan Rahim

发明人： Bruce B. Pedersen ,  Irfan Rahim

IPC分类号： H03K19/177 ,  H03K19/00 ,  H03K19/003

CPC分类号： H03K19/17752 ,  H03K19/003

摘要： In an exemplary embodiment, an apparatus includes a first set of circuit elements and a second set of circuit elements. The first set of circuit elements is used in a first configuration of the apparatus, and the second set of circuit elements is used in a second configuration of the apparatus. The first configuration of the apparatus is switched to the second configuration of the apparatus in order to improve reliability of the apparatus.

摘要翻译： 在示例性实施例中，装置包括第一组电路元件和第二组电路元件。 第一组电路元件用于装置的第一配置，并且第二组电路元件用于装置的第二配置。 该设备的第一配置被切换到设备的第二配置，以便提高设备的可靠性。

公开(公告)号：US07352610B1

公开(公告)日：2008-04-01

申请号：US11295815

申请日：2005-12-06

申请人： Bruce B. Pedersen ,  Irfan Rahim ,  Jeffrey T Watt

发明人： Bruce B. Pedersen ,  Irfan Rahim ,  Jeffrey T Watt

IPC分类号： G11C11/00

CPC分类号： G11C11/4125

摘要： Memory elements are provided that are immune to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements have nonlinear high-impedance two-terminal elements that restrict the flow of discharge currents during a particle strike. By lengthening the switching speed of the memory elements, the presence of the nonlinear high-impedance two-terminal elements prevents the states of the memory elements from flipping during discharge transients. The nonlinear high-impedance two-terminal elements may be formed from polysilicon p-n junction diodes, Schottky diodes, and other semiconductor structures. Data loading circuitry is provided to ensure that memory element arrays using the nonlinear high-impedance two-terminal elements can be loaded rapidly.

摘要翻译： 提供存储元件，当受到高能原子粒子撞击时，可以免受软错误不安事件的影响。 存储器元件具有非线性高阻抗二端元件，其限制了粒子撞击期间放电电流的流动。 通过延长存储元件的切换速度，非线性高阻抗二端元件的存在防止存储元件的状态在放电瞬变期间翻转。 非线性高阻抗二端元件可以由多晶硅p-n结二极管，肖特基二极管和其它半导体结构形成。 提供数据加载电路以确保使用非线性高阻抗二端元件的存储元件阵列可以快速加载。

公开(公告)号：US08698516B2

公开(公告)日：2014-04-15

申请号：US13214144

申请日：2011-08-19

申请人： Irfan Rahim ,  Jeffrey T. Watt ,  Richard G. Cliff ,  Andy L. Lee ,  Ping-Chen Liu

发明人： Irfan Rahim ,  Jeffrey T. Watt ,  Richard G. Cliff ,  Andy L. Lee ,  Ping-Chen Liu

IPC分类号： H03K17/16

CPC分类号： H03K19/17784 ,  H03K19/17792

摘要： A field programmable gate array (FPGA) includes a set of monitor circuits adapted to provide indications of process, voltage, and temperature for at least one circuit in the FPGA, and a controller adapted to derive a range of body-bias values for the at least one circuit from the indications of process, voltage, and temperature for the at least one circuit. The FPGA further includes a body-bias generator adapted to provide a body-bias signal to at least one transistor in the at least one circuit. The body-bias signal has a value within the range of body-bias values.

摘要翻译： 现场可编程门阵列（FPGA）包括一组监视器电路，其适于为FPGA中的至少一个电路提供过程，电压和温度的指示，以及控制器，其适于导出所述at的至少一个电路的体偏值的范围 用于至少一个电路的过程，电压和温度的指示的至少一个电路。 FPGA还包括体偏置发生器，其适于向至少一个电路中的至少一个晶体管提供体偏置信号。 体偏置信号具有在体偏值范围内的值。

公开(公告)号：US08643108B2

公开(公告)日：2014-02-04

申请号：US13214102

申请日：2011-08-19

申请人： Irfan Rahim ,  Jeffrey T. Watt ,  Yanzhong Xu ,  Lin-Shih Liu

发明人： Irfan Rahim ,  Jeffrey T. Watt ,  Yanzhong Xu ,  Lin-Shih Liu

IPC分类号： H01L27/12 ,  H01L21/336

CPC分类号： H01L29/7851 ,  H01L21/761 ,  H01L29/66795

摘要： One embodiment relates to a buffered transistor device. The device includes a buffered vertical fin-shaped structure formed in a semiconductor substrate. The vertical fin-shaped structure includes at least an upper semiconductor layer, a buffer region, and at least part of a well region. The buffer region has a first doping polarity, and the well region has a second doping polarity which is opposite to the first doping polarity. At least one p-n junction that at least partially covers a horizontal cross section of the vertical fin-shaped structure is formed between the buffer and well regions. Other embodiments, aspects, and features are also disclosed.

摘要翻译： 一个实施例涉及缓冲晶体管器件。 该器件包括形成在半导体衬底中的缓冲的垂直鳍状结构。 垂直鳍状结构至少包括上半导体层，缓冲区和阱区​​的至少一部分。 缓冲区具有第一掺杂极性，并且阱区具有与第一掺杂极性相反的第二掺杂极性。 在缓冲区和阱区​​之间形成至少部分覆盖垂直鳍状结构的水平横截面的至少一个p-n结。 还公开了其它实施例，方面和特征。

公开(公告)号：US08482963B1

公开(公告)日：2013-07-09

申请号：US12629831

申请日：2009-12-02

申请人： Jun Liu ,  Yanzhong Xu ,  Shankar Sinha ,  Shih-Lin S. Lee ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar ,  Qi Xiang ,  Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  Srinivas Perisetty

发明人： Jun Liu ,  Yanzhong Xu ,  Shankar Sinha ,  Shih-Lin S. Lee ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar ,  Qi Xiang ,  Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  Srinivas Perisetty

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

摘要翻译： 不对称晶体管可以通过在晶体管的一个源极 - 漏极端子上而不是另一个产生凹穴注入来形成。 也可以使用具有不同功函数的第一和第二栅极导体的双栅结构来形成非对称晶体管。 可以通过堆叠相同通道类型的两个晶体管串联形成堆叠晶体管。 两个晶体管中的每一个的源极 - 漏极端子之一连接到公共节点。 两个晶体管的栅极也连接在一起。 两个晶体管可以具有不同的阈值电压。 位于堆叠晶体管中较高的晶体管的阈值电压可以具有比堆叠晶体管中的另一个晶体管更低的阈值电压。 堆叠的晶体管可用于减少诸如存储器单元的电路中的漏电流。 不对称晶体管也可用于存储器单元中以减少泄漏。

公开(公告)号：US20130043902A1

公开(公告)日：2013-02-21

申请号：US13214144

申请日：2011-08-19

申请人： Irfan Rahim ,  Jeffrey T. Watt ,  Richard G. Cliff ,  Andy L. Lee ,  Ping-Chen Liu

发明人： Irfan Rahim ,  Jeffrey T. Watt ,  Richard G. Cliff ,  Andy L. Lee ,  Ping-Chen Liu

IPC分类号： H03K19/177

CPC分类号： H03K19/17784 ,  H03K19/17792

摘要： A field programmable gate array (FPGA) includes a set of monitor circuits adapted to provide indications of process, voltage, and temperature for at least one circuit in the FPGA, and a controller adapted to derive a range of body-bias values for the at least one circuit from the indications of process, voltage, and temperature for the at least one circuit. The FPGA further includes a body-bias generator adapted to provide a body-bias signal to at least one transistor in the at least one circuit. The body-bias signal has a value within the range of body-bias values.

摘要翻译： 现场可编程门阵列（FPGA）包括一组监视器电路，其适于为FPGA中的至少一个电路提供过程，电压和温度的指示，以及控制器，其适于导出针对 用于至少一个电路的过程，电压和温度的指示的至少一个电路。 FPGA还包括体偏置发生器，其适于向至少一个电路中的至少一个晶体管提供体偏置信号。 体偏置信号具有在体偏值范围内的值。

公开(公告)号：US07800402B1

公开(公告)日：2010-09-21

申请号：US11982865

申请日：2007-11-05

申请人： Irfan Rahim ,  Sriram Muthukumar ,  William Bradley Vest ,  Myron Wai Wong

发明人： Irfan Rahim ,  Sriram Muthukumar ,  William Bradley Vest ,  Myron Wai Wong

IPC分类号： H03K19/173 ,  G06F7/38

CPC分类号： H03K19/17736 ,  H03K19/17728 ,  H03K19/1778

摘要： A programmable logic device integrated circuit or other integrated circuit may have logic circuitry that produces data signals. The data signals may be routed to other logic circuits through interconnects. The interconnects may be programmable. A level recovery circuit may be used at the end of each interconnect line to strengthen the transmitted data signal. The level recovery circuit that is attached to a given interconnect line may produce true and complementary versions of the data signal that is on that interconnect line. Level shifting circuitry may be provided to boost the data signals on the interconnects. Each interconnect line may have a level shifter circuit that receives the true and complementary versions of a data signal and that produces corresponding boosted true and complementary versions of the data signal. The boosted signals may be provided to the control inputs of complementary-metal-oxide-semiconductor transistor pass gates in programmable look-up table circuitry.

摘要翻译： 可编程逻辑器件集成电路或其他集成电路可以具有产生数据信号的逻辑电路。 数据信号可以通过互连路由到其他逻辑电路。 互连可以是可编程的。 可以在每条互连线的末端使用电平恢复电路，以加强传输的数据信号。 连接到给定互连线的电平恢复电路可以产生在该互连线上的数据信号的真实和互补版本。 可以提供电平移位电路以升高互连上的数据信号。 每个互连线可以具有电平移位器电路，其接收数据信号的真实和互补版本并且产生数据信号的相应增强的真实和互补版本。 升压的信号可以提供给可编程查找表电路中的互补金属氧化物半导体晶体管栅极的控制输入。

公开(公告)号：US20080169836A1

公开(公告)日：2008-07-17

申请号：US11653001

申请日：2007-01-12

申请人： Irfan Rahim ,  Andy L. Lee ,  Myron Wai Wong ,  William Bradley Vest ,  Jeffrey T. Watt

发明人： Irfan Rahim ,  Andy L. Lee ,  Myron Wai Wong ,  William Bradley Vest ,  Jeffrey T. Watt

IPC分类号： H03K19/094 ,  G11C5/02

CPC分类号： H03K19/1776 ,  G11C11/401 ,  G11C11/404 ,  G11C14/00 ,  H03K19/1778

摘要： Integrated circuits such as programmable logic device integrated circuits are provided that have configuration random-access memory elements. The configuration random-access memory elements are loaded with configuration data to customize programmable logic on the integrated circuits. Each memory element has a capacitor that stores data for that memory element. A pair of cross-coupled inverters are connected to the capacitor. The inverters ensure that the memory elements produce output control signals with voltages than range from one power supply rail to another. Each configuration random-access memory element may have a clear transistor. The capacitor may be formed in a dielectric layer that lies above the transistors of the inverters, the address transistor, and the clear transistor. The inverters may be powered with an elevated power supply voltage.

摘要翻译： 提供了诸如可编程逻辑器件集成电路的集成电路，其具有配置随机存取存储器元件。 配置随机存取存储器元件装载有配置数据以在集成电路上定制可编程逻辑。 每个存储器元件具有存储该存储器元件的数据的电容器。 一对交叉耦合的反相器连接到电容器。 逆变器确保存储元件产生的输出控制信号的电压低于从一个电源轨到另一个电源的范围。 每个配置随机存取存储器元件可以具有透明晶体管。 电容器可以形成在位于反相器，地址晶体管和透明晶体管的晶体管之上的电介质层中。 逆变器可以用升高的电源电压供电。