公开(公告)号：US5897379A

公开(公告)日：1999-04-27

申请号：US995112

申请日：1997-12-19

申请人： Bruce Dale Ulrich ,  Tue Nguyen ,  Masato Kobayashi

发明人： Bruce Dale Ulrich ,  Tue Nguyen ,  Masato Kobayashi

IPC分类号： C23F1/02 ,  C23F1/18 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/3213 ,  B44C1/22 ,  H01L21/308

CPC分类号： H01L21/32134 ,  C23F1/18 ,  H01L21/02063 ,  H01L21/02087 ,  H01L21/3212 ,  H01L21/6708

摘要： A method of using diluted nitric acid and an edge bead removal tool to remove copper from the perimeter of a semiconductor wafer is provided. In one embodiment, sensitive areas of the wafer are covered with photoresist, and the wafer perimeter cleared of photoresist, before the acid is applied. In another embodiment, sensitive areas of the wafer are protected with water spray as the copper etchant is applied. In a third embodiment, the nitric acid is applied to clear the wafer perimeter of copper before a chemical mechanical polishing (CMP) is performed on the layer of deposited copper. The excess thickness of copper protects copper interconnection structures from reacting with the copper etchant. All these methods permit copper to be removed at a low enough temperature that copper oxides are not formed. A semiconductor wafer cleaned of copper in accordance with the above-described method, and a system for low temperature copper removal is also provided.

摘要翻译： 提供了使用稀硝酸和边缘珠除去工具从半导体晶片的周边去除铜的方法。 在一个实施例中，在施加酸之前，晶片的敏感区域被光致抗蚀剂覆盖，并且晶片外围的光致抗蚀剂被清除。 在另一个实施例中，当施加铜蚀刻剂时，晶片的敏感区域被水喷雾保护。 在第三实施例中，在对沉积的铜层进行化学机械抛光（CMP）之前，施加硝酸以清除铜的晶片周边。 铜的过剩厚度保护铜互连结构不与铜蚀刻剂反应。 所有这些方法允许铜在没有形成铜氧化物的足够低的温度下被去除。 还提供了根据上述方法清洁铜的半导体晶片和用于低温铜去除的系统。

公开(公告)号：US06020639A

公开(公告)日：2000-02-01

申请号：US223927

申请日：1998-12-31

申请人： Bruce Dale Ulrich ,  Tue Nguyen ,  Masato Kobayashi

发明人： Bruce Dale Ulrich ,  Tue Nguyen ,  Masato Kobayashi

IPC分类号： C23F1/02 ,  C23F1/18 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/3213 ,  H01L23/48

CPC分类号： H01L21/32134 ,  C23F1/18 ,  H01L21/02063 ,  H01L21/02087 ,  H01L21/3212 ,  H01L21/6708

摘要： A method of using diluted nitric acid and an edge bead removal tool to remove copper from the perimeter of a semiconductor wafer is provided. In one embodiment, sensitive areas of the wafer are covered with photoresist, and the wafer perimeter cleared of photoresist, before the acid is applied. In another embodiment, sensitive areas of the wafer are protected with water spray as the copper etchant is applied. In a third embodiment, the nitric acid is applied to clear the wafer perimeter of copper before a chemical mechanical polishing (CMP) is performed on the layer of deposited copper. The excess thickness of copper protects copper interconnection structures from reacting with the copper etchant. All these methods permit copper to be removed at a low enough temperature that copper oxides are not formed. A semiconductor wafer cleaned of copper in accordance with the above-described method, and a system for low temperature copper removal is also provided.

摘要翻译： 提供了使用稀硝酸和边缘珠除去工具从半导体晶片的周边去除铜的方法。 在一个实施例中，在施加酸之前，晶片的敏感区域被光致抗蚀剂覆盖，并且晶片外围的光致抗蚀剂被清除。 在另一个实施例中，当施加铜蚀刻剂时，晶片的敏感区域被水喷雾保护。 在第三实施例中，在对沉积的铜层进行化学机械抛光（CMP）之前，施加硝酸以清除铜的晶片周边。 铜的过剩厚度保护铜互连结构不与铜蚀刻剂反应。 所有这些方法允许铜在没有形成铜氧化物的足够低的温度下被去除。 还提供了根据上述方法清洁铜的半导体晶片和用于低温铜去除的系统。

公开(公告)号：US5914202A

公开(公告)日：1999-06-22

申请号：US660870

申请日：1996-06-10

申请人： Tue Nguyen ,  Bruce Dale Ulrich ,  David Russell Evans

发明人： Tue Nguyen ,  Bruce Dale Ulrich ,  David Russell Evans

IPC分类号： G03F1/00 ,  G03F1/29 ,  H01L21/469 ,  G03F9/00

CPC分类号： G03F1/29 ,  G03F1/50

摘要： A method is providing for making a multi-level reticle which transmits a plurality of incident light intensities, which in turn, are used to form a plurality of thicknesses in a photoresist profile. A partially transmitting film, used as one of the layers of the reticle, is able to provide an intermediate intensity of phase shifted light. The intermediate intensity light has an intensity approximately midway between the intensity of the unattenuated light passing through the reticle substrate layer, and the totally attenuated light blocked by an opaque layer of the reticle. The exposed photoresist receives light at two intensities to form a via hole in the resist in response to the higher intensity light, and a connecting line to the via at an intermediate level of the photoresist in response to the intermediate light intensity. A method for forming the multi-level resist profile from the multi-level reticle is provided as well as a multi-level reticle apparatus.

摘要翻译： 一种提供制造多层掩模版的方法，其传输多个入射光强度，其又被用于在光致抗蚀剂轮廓中形成多个厚度。 用作掩模版之一的部分透射膜能够提供相移光的中等强度。 中间强度光在通过标线基底层的未衰减光的强度与由掩模版的不透明层阻挡的完全衰减的光之间的强度近似强度。 暴露的光致抗蚀剂以两个强度接收光，以响应于较高强度的光而在抗蚀剂中形成通孔，以及响应于中间光强度而在光致抗蚀剂的中间水平处的通孔的连接线。 提供了一种从多层掩膜形成多层抗蚀剂图案的方法以及多层掩模版设备。

公开(公告)号：US5821169A

公开(公告)日：1998-10-13

申请号：US692379

申请日：1996-08-05

申请人： Tue Nguyen ,  Chien-Hsiung Peng ,  Bruce Dale Ulrich

发明人： Tue Nguyen ,  Chien-Hsiung Peng ,  Bruce Dale Ulrich

IPC分类号： H01L21/302 ,  G03F7/00 ,  H01L21/027 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L21/00 ,  B44C1/22

CPC分类号： H01L21/76811 ,  G03F7/00 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76813 ,  H01L2221/1021

摘要： A method is provided for forming intermediate levels in an integrated circuit dielectric during a damascene process using a hard mask layer to transfer the pattern of a photoresist mask having at least one intermediate thickness. The dielectric is covered with a hard mask layer, and the hard mask layer is covered with the photoresist mask. The photoresist mask pattern is transferred into the hard mask pattern so that the hard mask pattern has at least one intermediate thickness. The method forms an interconnect to a first depth in the dielectric through an opening in the hard mask pattern. The hard mask pattern is partially etched away in the area of the intermediate thickness to reveal a second dielectric surface area. The second dielectric surface area is etched to a second depth, less than the first depth. In this manner, vias can be formed to the first depth, and lines can be formed at a second depth to intersect the vias. The use of a relatively thin hard mask pattern reduces the degradation of vertical surface features, due to faceting, which generally occurs with the use of a thicker photoresist pattern. The method of the present invention allows a multi-level damascene process to be used to form features with relatively small geometries in the dielectric.

摘要翻译： 提供一种用于在镶嵌工艺期间在集成电路电介质中形成中间层的方法，其中使用硬掩模层来传递具有至少一个中间厚度的光致抗蚀剂掩模的图案。 电介质用硬掩模层覆盖，并且硬掩模层被光致抗蚀剂掩模覆盖。 将光致抗蚀剂掩模图案转印到硬掩模图案中，使得硬掩模图案具有至少一个中间厚度。 该方法通过硬掩模图案中的开口形成到电介质中的第一深度的互连。 硬掩模图案在中间厚度的区域中被部分地蚀刻掉以露出第二电介质表面积。 第二电介质表面积被蚀刻到比第一深度小的第二深度。 以这种方式，可以将通孔形成为第一深度，并且可以在第二深度处形成线以与通孔相交。 使用相对薄的硬掩模图案由于刻面而减少垂直表面特征的劣化，这通常通过使用较厚的光致抗蚀剂图案而发生。 本发明的方法允许使用多层镶嵌工艺来形成电介质中具有较小几何形状的特征。

公开(公告)号：US5936707A

公开(公告)日：1999-08-10

申请号：US8362

申请日：1998-01-16

申请人： Tue Nguyen ,  Bruce Dale Ulrich ,  David Russell Evans

发明人： Tue Nguyen ,  Bruce Dale Ulrich ,  David Russell Evans

IPC分类号： G03F1/00 ,  G03F1/29 ,  H01L21/469 ,  G03B27/00 ,  G03B27/04 ,  G03B27/28

CPC分类号： G03F1/29 ,  G03F1/50

摘要： A method is providing for making a multi-level reticle which transmits a plurality of incident light intensities, which in turn, are used to form a plurality of thicknesses in a photoresist profile. A partially transmitting film, used as one of the layers of the reticle, is able to provide an intermediate intensity light. The intermediate intensity light has an intensity approximately midway between the intensity of the unattenuated light passing through the reticle substrate layer, and the totally attenuated light blocked by an opaque layer of the reticle. The exposed photoresist receives light at two intensities to form a via hole in the resist in response to the higher intensity light, and a connecting line to the via at an intermediate level of the photoresist in response to the intermediate light intensity. A method for forming the multi-level resist profile from the multi-level reticle is provided as well as a multi-level reticle apparatus.

摘要翻译： 一种提供制造多层掩模版的方法，其传输多个入射光强度，其又被用于在光致抗蚀剂轮廓中形成多个厚度。 用作掩模版之一的部分透射膜能够提供中等强度的光。 中间强度光在通过标线基底层的未衰减光的强度与由掩模版的不透明层阻挡的完全衰减的光之间的强度近似强度。 暴露的光致抗蚀剂以两个强度接收光，以响应于较高强度的光而在抗蚀剂中形成通孔，以及响应于中间光强度而在光致抗蚀剂的中间水平处的通孔的连接线。 提供了一种从多层掩膜形成多层抗蚀剂图案的方法以及多层掩模版设备。

公开(公告)号：US6043164A

公开(公告)日：2000-03-28

申请号：US665014

申请日：1996-06-10

申请人： Tue Nguyen ,  Sheng Teng Hsu ,  Jer-shen Maa ,  Bruce Dale Ulrich ,  Chien-Hsiung Peng

发明人： Tue Nguyen ,  Sheng Teng Hsu ,  Jer-shen Maa ,  Bruce Dale Ulrich ,  Chien-Hsiung Peng

IPC分类号： G03F7/36 ,  H01L21/027 ,  H01L21/033 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/768

CPC分类号： H01L21/31144 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/0274 ,  H01L21/0334 ,  H01L2221/1021

摘要： A method is provided for forming an intermediate level in an integrated circuit dielectric during a damascene process using a photoresist mask having an intermediate thickness. The method forms an interconnect to a first depth in the dielectric through an opening in the photoresist pattern. The photoresist profile is partially etched away in the area of the intermediate thickness to reveal a second dielectric surface area. The second dielectric surface area is then etched to a second depth less than the first depth. In this manner, vias can be formed to the first depth, and lines can be formed at a second depth to intersect the vias. The method of the present invention allows a dual damascene process to be performed with a single step of photoresist formation.

摘要翻译： 提供一种用于在使用具有中间厚度的光致抗蚀剂掩模的镶嵌工艺期间在集成电路电介质中形成中间电平的方法。 该方法通过光致抗蚀剂图案中的开口形成到电介质中的第一深度的互连。 光致抗蚀剂轮廓在中间厚度的区域被部分地蚀刻掉以露出第二电介质表面积。 然后将第二电介质表面积蚀刻到小于第一深度的第二深度。 以这种方式，可以将通孔形成为第一深度，并且可以在第二深度处形成线以与通孔相交。 本发明的方法允许通过单步形成光致抗蚀剂来进行双镶嵌工艺。

公开(公告)号：US5906910A

公开(公告)日：1999-05-25

申请号：US8257

申请日：1998-01-16

申请人： Tue Nguyen ,  Bruce Dale Ulrich ,  David Russell Evans

发明人： Tue Nguyen ,  Bruce Dale Ulrich ,  David Russell Evans

IPC分类号： G03F1/00 ,  G03F1/29 ,  H01L21/469 ,  G03C5/00

CPC分类号： G03F1/29 ,  G03F1/50

摘要： A method is providing for making a multi-level reticle which transmits a plurality of incident light intensities, which in turn, are used to form a plurality of thicknesses in a photoresist profile. A partially transmitting film, used as one of the layers of the reticle, is able to provide an intermediate intensity light. The intermediate intensity light has an intensity approximately midway between the intensity of the unattenuated light passing through the reticle substrate layer, and the totally attenuated light blocked by an opaque layer of the reticle. The exposed photoresist receives light at two intensities to form a via hole in the resist in response to the higher intensity light, and a connecting line to the via at an intermediate level of the photoresist in response to the intermediate light intensity. A method for forming the multi-level resist profile from the multi-level reticle is provided as well as a multi-level reticle apparatus.

摘要翻译： 一种提供制造多层掩模版的方法，其传输多个入射光强度，其又被用于在光致抗蚀剂轮廓中形成多个厚度。 用作掩模版之一的部分透射膜能够提供中等强度的光。 中间强度光在通过标线基底层的未衰减光的强度与由掩模版的不透明层阻挡的完全衰减的光之间的强度近似强度。 暴露的光致抗蚀剂以两个强度接收光，以响应于较高强度的光而在抗蚀剂中形成通孔，以及响应于中间光强度而在光致抗蚀剂的中间水平处的通孔的连接线。 提供了一种从多层掩膜形成多层抗蚀剂图案的方法以及多层掩模版设备。

公开(公告)号：US5767301A

公开(公告)日：1998-06-16

申请号：US786546

申请日：1997-01-21

申请人： Yoshihide Senzaki ,  Masato Kobayashi ,  Lawrence J. Charneski ,  Tue Nguyen

发明人： Yoshihide Senzaki ,  Masato Kobayashi ,  Lawrence J. Charneski ,  Tue Nguyen

IPC分类号： C07F7/18 ,  C23C16/18 ,  H01L21/28 ,  H01L21/285 ,  C07F1/08

CPC分类号： C23C16/18 ,  C07F7/1836 ,  C07F7/184 ,  C07F7/1844

摘要： A method is provided for applying chemical vapor deposition (CVD) copper (Cu) to integrated circuit substrates using a Cu(hfac)(ligand) precursor with a silylolefin ligand including combinations of C1-C8 alkyl groups with at least one C2-C8 alkyloxy group. The alkyloxy groups include, ethoxy, propoxy, butoxy, pentyloxy, hexyloxy, heptyloxy, octyloxy, and aryloxy, while the alkyl groups include methyl, ethyl, propyl, butyl, pentyl, hexyl, heptyl, octyl, and aryl. The oxygen atoms of the alkyloxy groups, and the long carbon chains of both the alkyl and alkyloxy groups, increase the stability of the precursor by contributing electrons to the Cu(hfac) complex. The improved bond helps insure that the ligand separates from the (hfac)Cu complex at consistent temperatures when Cu is to be deposited. Combinations of alkyloxy and alkyl groups allow the molecular weight of the precursor to be manipulated so that the volatility of the precursor is adjustable for specific process scenarios. Other embodiments provide a precursor blend made from additional silylolefins, hexafluoroacetylacetone (H-hfac), H-hfac dihydrate, and water, either separately, or in combinations, to enhance deposition rate, conductivity, and precursor stability. A Cu precursor compound including silylolefin ligands having at least one alkyloxy group is also provided. Combinations of ethyl groups with ethoxy groups are specifically disclosed.

摘要翻译： 提供了一种用于使用Cu（hfac）（配体）前体将金属化学气相沉积（CVD）铜（Cu）施加到集成电路衬底的方法，所述Cu（hfac）（配体）前体具有含有C 1 -C 8烷基与至少一个C 2 -C 8烷氧基 组。 烷氧基包括乙氧基，丙氧基，丁氧基，戊氧基，己氧基，庚氧基，辛氧基和芳氧基，而烷基包括甲基，乙基，丙基，丁基，戊基，己基，庚基，辛基和芳基。 烷基氧基和烷基和烷氧基的长碳链的氧原子通过向Cu（hfac）络合物贡献电子而增加前体的稳定性。 当Cu沉积时，改进的键有助于确保配体在恒定温度下与（hfac）Cu络合物分离。 烷氧基和烷基的组合允许操纵前体的分子量，使得前体的挥发性对于具体的工艺情况是可调节的。 其他实施方案提供由另外的水溶性烯烃，六氟乙酰丙酮（H-hfac），H-hfac二水合物和水分别或组合地制备的前体共混物，以增强沉积速率，导电性和前体稳定性。 还提供了包含具有至少一个烷氧基的硅单元配体的Cu前体化合物。 具体公开乙基与乙氧基的组合。

公开(公告)号：US5744192A

公开(公告)日：1998-04-28

申请号：US745562

申请日：1996-11-08

申请人： Tue Nguyen ,  Yoshihide Senzaki ,  Masato Kobayashi ,  Lawrence J. Charneski ,  Sheng Teng Hsu

发明人： Tue Nguyen ,  Yoshihide Senzaki ,  Masato Kobayashi ,  Lawrence J. Charneski ,  Sheng Teng Hsu

IPC分类号： C01G3/00 ,  C23C16/18 ,  C23C16/448 ,  C23C16/52 ,  H01L21/28 ,  H01L21/285 ,  H01L21/60 ,  B05D5/12 ,  C23C16/04

CPC分类号： C23C16/4481 ,  C23C16/18 ,  H01L2924/0002

摘要： A method of blending water vapor with volatile Cu(hfac)TMVS (copper hexafluoroacetylacetonate trimethylvinylsilane) is provided which improves the deposition rate of Cu, without degrading the resistivity of the Cu deposited upon an integrated circuit surface. The method of the present invention uses a relatively small amount of water vapor, approximately 0.3 to 3% of the total pressure of the system in which chemical vapor deposition (CVD) Cu is applied. The method specifies the flow rates of the liquid precursor, carrier gas, and liquid water. The method also specifies the pressures of the vaporized precursor, vaporized precursor blend including carrier gas and water vapor. In addition, the temperatures of the vaporizers, chamber walls, and IC surfaces are disclosed. A Cu precursor blend is also provided comprising vaporized Cu(hfac)TMVS and water vapor. The ratio of water vapor pressure to vaporized precursor is approximately 0.5 to 5%. Further, an IC surface covered with Cu applied with a Cu precursor blend including vaporized Cu(hfac)TMVS and water vapor, with the above mentioned ratio of water vapor pressure to volatile Cu(hfac)TMVS pressure, is provided.

摘要翻译： 提供了将水蒸汽与挥发性Cu（hfac）TMVS（六氟乙酰丙酮酸铜三甲基乙烯基硅烷）共混的方法，其改善了Cu的沉积速率，而不降低沉积在集成电路表面上的Cu的电阻率。 本发明的方法使用相对少量的水蒸气，其中施加化学气相沉积（CVD）Cu的系统的总压力的大约0.3至3％。 该方法规定了液体前体，载气和液态水的流量。 该方法还规定了蒸发的前体，蒸发的前体共混物包括载气和水蒸气的压力。 此外，公开了蒸发器，室壁和IC表面的温度。 还提供了包含蒸发的Cu（hfac）TMVS和水蒸气的Cu前体共混物。 水蒸气压与汽化前体的比率约为0.5〜5％。 此外，提供了用Cu涂覆Cu包含蒸发的Cu（hfac）TMVS和水蒸气的Cu前体共混物的IC表面，具有上述的水蒸气压与挥发性Cu（hfac）TMVS压力的比率。

公开(公告)号：US6090960A

公开(公告)日：2000-07-18

申请号：US779640

申请日：1997-01-07

申请人： Yoshihide Senzaki ,  Lawrence J. Charneski ,  Masato Kobayashi ,  Tue Nguyen

发明人： Yoshihide Senzaki ,  Lawrence J. Charneski ,  Masato Kobayashi ,  Tue Nguyen

IPC分类号： C07F7/18 ,  C23C16/18 ,  H01L21/28 ,  H01L21/285 ,  C07F7/08 ,  C07F1/08

CPC分类号： C23C16/18 ,  C07F7/1836

摘要： A method of applying chemical vapor deposition (CVD) copper (Cu) to integrated circuit substrates using a precursor with either a dimethoxymethylvinylsilane (dmomvs), or methoxydimethylvinylsilane (modmvs), silylolefin ligand bonded to (hfac)Cu is provided. The dmomvs ligand is able to provide the electrons of oxygen atoms from two methoxy groups to improve the bond between the ligand and the (hfac)Cu complex. The improved bond helps insure that the ligand separates from the (hfac)Cu complex at consistent temperatures when Cu is to be deposited. In situations where a precursor having a smaller molecular weight is desired, the modmvs ligand is used to provide electrons from the oxygen atom of the single methoxy group. In the preferred embodiment, water vapor is added to the volatile precursor to improve the conductivity of the deposited Cu. Other embodiments provide a precursor blend made from additional silylolefins, hexafluoroacetylacetone (H-hfac), and water, either separately, or in combinations, to enhance deposition rate, conductivity, and precursor stability. A Cu precursor compound including the dmomvs and modmvs ligands with (hfac)Cu is also provided.

摘要翻译： 提供了使用具有二甲氧基甲基乙烯基硅烷（dmomvs）或甲氧基二甲基乙烯基硅烷（modmvs），与（hfac）Cu键合的硅氧烷配体的前体将化学气相沉积（CVD）铜（Cu）施加到集成电路基板的方法。 dmomvs配体能够提供来自两个甲氧基的氧原子的电子，以改善配体和（hfac）Cu络合物之间的键。 当Cu沉积时，改进的键有助于确保配体在恒定温度下与（hfac）Cu络合物分离。 在需要具有较小分子量的前体的情况下，modmvs配体用于从单个甲氧基的氧原子提供电子。 在优选的实施方案中，将水蒸汽加入到挥发性前体中以改善沉积的Cu的导电性。 其它实施方案提供由另外的水溶性烯烃，六氟乙酰丙酮（H-hfac）和水单独或组合地制备的前体共混物，以增强沉积速率，导电性和前体稳定性。 还提供了包含具有（hfac）Cu的dmomvs和modmvs配体的Cu前体化合物。