公开(公告)号：US6043164A

公开(公告)日：2000-03-28

申请号：US665014

申请日：1996-06-10

申请人： Tue Nguyen ,  Sheng Teng Hsu ,  Jer-shen Maa ,  Bruce Dale Ulrich ,  Chien-Hsiung Peng

发明人： Tue Nguyen ,  Sheng Teng Hsu ,  Jer-shen Maa ,  Bruce Dale Ulrich ,  Chien-Hsiung Peng

IPC分类号： G03F7/36 ,  H01L21/027 ,  H01L21/033 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/768

CPC分类号： H01L21/31144 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/0274 ,  H01L21/0334 ,  H01L2221/1021

摘要： A method is provided for forming an intermediate level in an integrated circuit dielectric during a damascene process using a photoresist mask having an intermediate thickness. The method forms an interconnect to a first depth in the dielectric through an opening in the photoresist pattern. The photoresist profile is partially etched away in the area of the intermediate thickness to reveal a second dielectric surface area. The second dielectric surface area is then etched to a second depth less than the first depth. In this manner, vias can be formed to the first depth, and lines can be formed at a second depth to intersect the vias. The method of the present invention allows a dual damascene process to be performed with a single step of photoresist formation.

摘要翻译： 提供一种用于在使用具有中间厚度的光致抗蚀剂掩模的镶嵌工艺期间在集成电路电介质中形成中间电平的方法。 该方法通过光致抗蚀剂图案中的开口形成到电介质中的第一深度的互连。 光致抗蚀剂轮廓在中间厚度的区域被部分地蚀刻掉以露出第二电介质表面积。 然后将第二电介质表面积蚀刻到小于第一深度的第二深度。 以这种方式，可以将通孔形成为第一深度，并且可以在第二深度处形成线以与通孔相交。 本发明的方法允许通过单步形成光致抗蚀剂来进行双镶嵌工艺。

公开(公告)号：US06339245B1

公开(公告)日：2002-01-15

申请号：US09378653

申请日：1999-08-20

申请人： Jer-Shen Maa ,  Sheng Teng Hsu ,  Chien-Hsiung Peng

发明人： Jer-Shen Maa ,  Sheng Teng Hsu ,  Chien-Hsiung Peng

IPC分类号： H01L2976

CPC分类号： H01L29/6659 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6656

摘要： A method of forming a temporary overhang structure to shield the source/drain edges near the gate electrode from the deposition of silicidation metal is provided. The growth of silicide on the source/drain regions remains controlled, without the presence of silicidation metal on the gate electrode sidewalls near the source/drain edges. The resulting silicide layer does not have edge growths interfering with the source/drain junction areas. The overhang structure is formed by covering the gate electrode with two insulators having differing etch selectivities. The top insulator is anisotropically etched so that only the top insulator covering the gate electrode vertical sidewalls remains. The exposed bottom insulator is isotropically etched to form a gap between the top insulator and the source/drain region surfaces. When silicidation metal is deposited, the gap prevents the deposition of metal between the gate electrode and the source/drain region surfaces. A transistor, with an overhang structure, fabricated by the above-mentioned procedure is also provided.

摘要翻译： 提供了形成临时突出结构以屏蔽栅电极附近的源/漏边缘与沉积硅化金属的方法。 源极/漏极区域上的硅化物的生长保持受控，而在源极/漏极边缘附近的栅电极侧壁上不存在硅化金属。 所得到的硅化物层不具有干扰源极/漏极结区域的边缘增长。 通过用具有不同蚀刻选择性的两个绝缘体覆盖栅电极来形成突出结构。 顶绝缘体被各向异性地蚀刻，使得仅覆盖覆盖栅电极垂直侧壁的顶绝缘体保留。 暴露的底部绝缘体被各向同性地蚀刻以在顶部绝缘体和源极/漏极区域表面之间形成间隙。 当沉积硅化金属时，间隙防止金属沉积在栅电极和源/漏区表面之间。 还提供了通过上述程序制造的具有突出结构的晶体管。

公开(公告)号：US06218249B1

公开(公告)日：2001-04-17

申请号：US09455588

申请日：1999-12-06

申请人： Jer-Shen Maa ,  Sheng Teng Hsu ,  Chien-Hsiung Peng

发明人： Jer-Shen Maa ,  Sheng Teng Hsu ,  Chien-Hsiung Peng

IPC分类号： H01L21336

CPC分类号： H01L21/28518 ,  H01L21/28052 ,  H01L29/665 ,  H01L29/6659

摘要： A process of forming silicide at uniform rates across the entire source/drain region is provided. A two-step annealing method permits the thickness of the silicide formed on the edge of a silicon electrode to be substantially the same as it is in the center of the electrode. A first, low temperature anneal begins the salicidation process across the source/drain electrode surface. The time and temperature are controlled so that the metal is only partially consumed. The annealing is interrupted to remove excess silicidation metal, especially the unreacted metal overlying oxide areas neighboring the silicon electrode. Then, the silicidation is completed at a higher temperature anneal. Because the excess metal has been removed, the resulting silicide layer is uniformly flat, permitting the transistor to be fabricated with shallow junction areas and low leakage currents. In one embodiment of the invention, the crystalline structure of source and drain surfaces is annihilated before the deposition of metal, to lower annealing temperatures and add precise control to the silicidation process. A transistor having a uniformly thick silicide layer, fabricated in accordance with the above-mentioned method, is also provided.

摘要翻译： 提供了在整个源极/漏极区域以均匀的速率形成硅化物的工艺。 两步退火方法允许形成在硅电极边缘上的硅化物的厚度与电极中心基本相同。 首先，低温退火开始跨越源/漏电极表面的盐析过程。 控制时间和温度，使得金属仅被部分消耗。 中断退火以去除过量的硅化金属，特别是覆盖与硅电极相邻的氧化物区域的未反应的金属。 然后，在较高温度的退火下完成硅化。 由于去除了多余的金属，所得到的硅化物层是均匀平坦的，从而允许晶体管被制造成具有浅结的区域和低的漏电流。 在本发明的一个实施例中，源极和漏极表面的晶体结构在金属沉积之前被消除，以降低退火温度并且增加对硅化工艺的精确控制。 还提供了具有根据上述方法制造的均匀厚的硅化物层的晶体管。

公开(公告)号：US6071782A

公开(公告)日：2000-06-06

申请号：US23383

申请日：1998-02-13

申请人： Jer-Shen Maa ,  Sheng Teng Hsu ,  Chien-Hsiung Peng

发明人： Jer-Shen Maa ,  Sheng Teng Hsu ,  Chien-Hsiung Peng

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/60 ,  H01L29/78 ,  H01L21/44

CPC分类号： H01L21/28518 ,  H01L29/665 ,  H01L21/28052 ,  H01L29/6659

摘要： A process of forming silicide at uniform rates across the entire source/drain region is provided. A two-step annealing method permits the thickness of the silicide formed on the edge of a silicon electrode to be substantially the same as it is in the center of the electrode. A first, low temperature anneal begins the salicidation process across the source/drain electrode surface. The time and temperature are controlled so that the metal is only partially consumed. The annealing is interrupted to remove excess silicidation metal, especially the unreacted metal overlying oxide areas neighboring the silicon electrode. Then, the silicidation is completed at a higher temperature anneal. Because the excess metal has been removed, the resulting silicide layer is uniformly flat, permitting the transistor to be fabricated with shallow junction areas and low leakage currents. In one embodiment of the invention, the crystalline structure of source and drain surfaces is annihilated before the deposition of metal, to lower annealing temperatures and add precise control to the silicidation process. A transistor having a uniformly thick silicide layer, fabricated in accordance with the above-mentioned method, is also provided.

摘要翻译： 提供了在整个源极/漏极区域以均匀的速率形成硅化物的工艺。 两步退火方法允许形成在硅电极边缘上的硅化物的厚度与电极中心基本相同。 首先，低温退火开始跨越源/漏电极表面的盐析过程。 控制时间和温度，使得金属仅被部分消耗。 中断退火以去除过量的硅化金属，特别是覆盖与硅电极相邻的氧化物区域的未反应的金属。 然后，在较高温度的退火下完成硅化。 由于去除了多余的金属，所得到的硅化物层是均匀平坦的，从而允许晶体管被制造成具有浅结的区域和低的漏电流。 在本发明的一个实施例中，源极和漏极表面的晶体结构在金属沉积之前被消除，以降低退火温度并且增加对硅化工艺的精确控制。 还提供了具有根据上述方法制造的均匀厚的硅化物层的晶体管。

公开(公告)号：US5989965A

公开(公告)日：1999-11-23

申请号：US23032

申请日：1998-02-13

申请人： Jer-Shen Maa ,  Sheng Teng Hsu ,  Chien-Hsiung Peng

发明人： Jer-Shen Maa ,  Sheng Teng Hsu ,  Chien-Hsiung Peng

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6656

摘要： A method of forming a temporary overhang structure to shield the source/drain edges near the gate electrode from the deposition of silicidation metal is provided. The growth of silicide on the source/drain regions remains controlled, without the presence of silicidation metal on the gate electrode sidewalls near the source/drain edges. The resulting silicide layer does not have edge growths interfering with the source/drain junction areas. The overhang structure is formed by covering the gate electrode with two insulators having differing etch selectivities. The top insulator is anisotropically etched so that only the top insulator covering the gate electrode vertical sidewalls remains. The exposed bottom insulator is isotropically etched to form a gap between the top insulator and the source/drain region surfaces. When silicidation metal is deposited, the gap prevents the deposition of metal between the gate electrode and the source/drain region surfaces. A transistor, with an overhang structure, fabricated by the above-mentioned procedure is also provided.

摘要翻译： 提供了形成临时突出结构以屏蔽栅电极附近的源/漏边缘与沉积硅化金属的方法。 源极/漏极区域上的硅化物的生长保持受控，而在源极/漏极边缘附近的栅电极侧壁上不存在硅化金属。 所得到的硅化物层不具有干扰源极/漏极结区域的边缘增长。 通过用具有不同蚀刻选择性的两个绝缘体覆盖栅电极来形成突出结构。 顶绝缘体被各向异性地蚀刻，使得仅覆盖覆盖栅电极垂直侧壁的顶绝缘体保留。 暴露的底部绝缘体被各向同性地蚀刻以在顶部绝缘体和源极/漏极区域表面之间形成间隙。 当沉积硅化金属时，间隙防止金属沉积在栅电极和源/漏区表面之间。 还提供了通过上述方法制造的具有突出结构的晶体管。

公开(公告)号：US07675056B2

公开(公告)日：2010-03-09

申请号：US11891574

申请日：2007-08-10

申请人： Jong-Jan Lee ,  Sheng Teng Hsu ,  Jer-Shen Maa ,  Douglas J. Tweet

发明人： Jong-Jan Lee ,  Sheng Teng Hsu ,  Jer-Shen Maa ,  Douglas J. Tweet

IPC分类号： H01L29/06 ,  H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/062 ,  H01L31/113 ,  H01L31/0232

CPC分类号： H01L31/1136 ,  H01L31/028 ,  H01L31/1808 ,  Y02E10/547

摘要： A floating body germanium (Ge) phototransistor and associated fabrication process are presented. The method includes: providing a silicon (Si) substrate; selectively forming an insulator layer overlying the Si substrate; forming an epitaxial Ge layer overlying the insulator layer using a liquid phase epitaxy (LPE) process; forming a channel region in the Ge layer; forming a gate dielectric, gate electrode, and gate spacers overlying the channel region; and, forming source/drain regions in the Ge layer. The LPE process involves encapsulating the Ge with materials having a melting temperature greater than a first temperature, and melting the Ge using a temperature lower than the first temperature. The LPE process includes: forming a dielectric layer overlying deposited Ge; melting the Ge; and, in response to cooling the Ge, laterally propagating an epitaxial growth front into the Ge from an underlying Si substrate surface.

摘要翻译： 提出了一种浮体锗（Ge）光电晶体管及其制造工艺。 该方法包括：提供硅（Si）衬底; 选择性地形成覆盖Si衬底的绝缘体层; 使用液相外延（LPE）工艺形成覆盖绝缘体层的外延Ge层; 在Ge层中形成沟道区; 形成覆盖所述沟道区的栅极电介质，栅电极和栅极间隔; 并且在Ge层中形成源/漏区。 LPE工艺包括用具有大于第一温度的熔化温度的材料包封Ge，并且使用低于第一温度的温度来熔化Ge。 LPE工艺包括：形成覆盖沉积Ge的介电层; 融化Ge; 并且响应于冷却Ge，将外延生长前沿从下面的Si衬底表面横向传播到Ge中。

公开(公告)号：US20080280426A1

公开(公告)日：2008-11-13

申请号：US11801210

申请日：2007-05-09

申请人： Tingkai Li ,  Douglas J. Tweet ,  Jer-Shen Maa ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Douglas J. Tweet ,  Jer-Shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L29/739 ,  H01L21/20

CPC分类号： C30B29/406 ,  C30B25/183 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/02642 ,  H01L21/02647 ,  H01L29/2003 ,  H01L29/267

摘要： A method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate and forms a first aluminum (Al)-containing film in compression overlying the Si substrate. Nano-column holes are formed in the first Al-containing film, which exposes regions of the underlying Si substrate. A layer of GaN layer is selectively grown from the exposed regions, covering the first Al-containing film. The GaN is grown using a lateral nanoheteroepitaxy overgrowth (LNEO) process. The above-mentioned processes are reiterated, forming a second Al-containing film in compression, forming nano-column holes in the second Al-containing film, and selectively growing a second GaN layer. Film materials such as Al2O3, Si1-xGex, InP, GaP, GaAs, AlN, AlGaN, or GaN, may be initially grown at a low temperature. By increasing the growth temperatures, a compressed layer of epitaxial GaN can be formed on a Si substrate.

摘要翻译： 提供了一种在硅（Si）和氮化镓（GaN）膜之间形成匹配的热膨胀界面的方法。 该方法提供（111）Si衬底并且在压缩覆盖Si衬底上形成第一含铝（Al）的膜。 在第一含Al膜中形成纳米柱孔，其暴露下面的Si衬底的区域。 从暴露区域选择性地生长GaN层，覆盖第一含Al膜。 使用横向纳米外延生长（LNEO）工艺生长GaN。 重复上述过程，在压缩中形成第二含Al膜，在第二含Al膜中形成纳米柱孔，并选择性地生长第二GaN层。 可以最初在低温下生长诸如Al 2 O 3 3，Si 1-x Ge x，InP，GaP，GaAs，AlN，AlGaN或GaN的膜材料。 通过增加生长温度，可以在Si衬底上形成外延GaN的压缩层。

公开(公告)号：US07351995B2

公开(公告)日：2008-04-01

申请号：US11894938

申请日：2007-08-22

申请人： Sheng Teng Hsu ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas J. Tweet

发明人： Sheng Teng Hsu ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas J. Tweet

IPC分类号： H01L29/06 ,  H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/062 ,  H01L31/113 ,  H01L31/0232

CPC分类号： H01L31/1136

摘要： A floating body germanium (Ge) phototransistor with a photo absorption threshold bias region, and an associated fabrication process are presented. The method includes: providing a p-doped Silicon (Si) substrate; selectively forming an insulator layer overlying a first surface of the Si substrate; forming an epitaxial Ge layer overlying the insulator layer; forming a channel region in the Ge layer; forming a gate dielectric, gate electrode, and gate spacers; forming source/drain (S/D) regions in the Ge layer; and, forming a photo absorption threshold bias region in the Ge layer, adjacent the channel region. In one aspect, the second S/D region has a length, longer than the first S/D length. The photo absorption threshold bias region underlies the second S/D region. Alternately, the second S/D region is separated from the channel by an offset, and the photo absorption threshold bias region is the offset in the Ge layer, after a light p-doping.

摘要翻译： 提出了具有光吸收阈值偏置区域的浮体锗（Ge）光电晶体管，以及相关的制造工艺。 该方法包括：提供p掺杂硅（Si）衬底; 选择性地形成覆盖在所述Si衬底的第一表面上的绝缘体层; 形成覆盖绝缘体层的外延Ge层; 在Ge层中形成沟道区; 形成栅极电介质，栅电极和栅极间隔物; 在Ge层中形成源极/漏极（S / D）区域; 并且在Ge层中形成邻近沟道区的光吸收阈值偏置区域。 在一个方面，第二S / D区域具有比第一S / D长度更长的长度。 光吸收阈值偏置区域位于第二S / D区域的下方。 或者，第二S / D区域与沟道分离偏移，光吸收阈值偏置区域是在光p掺杂之后的Ge层中的偏移。

公开(公告)号：US06780700B2

公开(公告)日：2004-08-24

申请号：US10035503

申请日：2001-10-25

申请人： Katsuji Iguchi ,  Sheng Teng Hsu ,  Yoshi Ono ,  Jer-shen Maa

发明人： Katsuji Iguchi ,  Sheng Teng Hsu ,  Yoshi Ono ,  Jer-shen Maa

IPC分类号： H01L218238

CPC分类号： H01L21/823814

摘要： A method of forming a MOS or CMOS device on a silicon substrate, includes preparing a substrate to contain conductive regions having device active areas therein; forming a gate electrode on the active areas; depositing and forming a gate electrode sidewall insulator layer on each gate electrode; implanting ions of a first type to form a source region and a drain region in one active area and implanting ions of a second type to form a source region and a drain region in the other active area.

摘要翻译： 一种在硅衬底上形成MOS器件或CMOS器件的方法，包括制备衬底以包含其中具有器件有源区的导电区; 在有源区上形成栅电极; 在每个栅电极上沉积和形成栅电极侧壁绝缘体层; 注入第一类型的离子以在一个有效区域中形成源极区域和漏极区域，并且注入第二类型的离子，以在另一个有源区域中形成源极区域和漏极区域。

公开(公告)号：US06746902B2

公开(公告)日：2004-06-08

申请号：US10062319

申请日：2002-01-31

申请人： Jer-Shen Maa ,  Douglas James Tweet ,  Sheng Teng Hsu

发明人： Jer-Shen Maa ,  Douglas James Tweet ,  Sheng Teng Hsu

IPC分类号： H01L2100

CPC分类号： H01L21/322 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02694 ,  Y10S438/933

摘要： A method of forming a SiGe layer having a relatively high Ge content includes preparing a silicon substrate; depositing a layer of SiGe to a thickness of between about 100 nm to 500 nm, wherein the Ge content of the SiGe layer is equal to or greater than 22%, by molecular weight; implanting H+ ions into the SiGe layer at a dose of between about 1·1016 cm−2 to 5·1016 cm−2, at an energy of between about 20 keV to 45 keV; thermal annealing the substrate and SiGe layer, to relax the SiGe layer, in an inert atmosphere at a temperature of between about 650° C. to 950° C. for between about 30 seconds and 30 minutes; and depositing a layer of tensile-strained silicon on the relaxed SiGe layer to a thickness of between about 5 nm to 30 nm.

摘要翻译： 形成Ge含量较高的SiGe层的方法包括制备硅衬底; 将SiGe层沉积至约100nm至500nm的厚度，其中SiGe层的Ge含量通过分子量等于或大于22％; 以约20keV至45keV之间的能量以约1.10 16 cm -2至5.10 16 cm -2的剂量将H +离子注入SiGe层; 热处理基板和SiGe层，以在约650℃至950℃的温度的惰性气氛中放松SiGe层约30秒至30分钟; 以及在弛豫的SiGe层上沉积拉伸应变硅层至约5nm至30nm的厚度。