公开(公告)号：US06535280B1

公开(公告)日：2003-03-18

申请号：US09944794

申请日：2001-08-31

申请人： Bruno La Fontaine ,  Jongwook Kye ,  Harry Levinson

发明人： Bruno La Fontaine ,  Jongwook Kye ,  Harry Levinson

IPC分类号： G01J100

CPC分类号： G03F9/7026 ,  G03F9/7049

摘要： An optical monitor includes a body having a first plurality of parallel, substantially opaque, spaced apart lines thereon, and the second plurality of parallel, substantially opaque, spaced apart lines thereon, with a relatively small angle between the first and second pluralities of lines. A an image of the lines of the first plurality thereof is provided on the semiconductor body, upon relative movement of the monitor toward and away from the semiconductor body, the line images move relative to the semiconductor body. The images of the lines of the second plurality thereof provided on the semiconductor body move in a different manner upon relative movement if the monitor toward and away from the semiconductor body: The moiré fringe formed on the semiconductor body from images of the first and second plurality of lines during such movement is analyzed in order to achieve proper focus of the image on the semiconductor body.

摘要翻译： 光学监视器包括主体，其上具有第一多个平行的，基本上不透明的间隔开的线，以及其上的第二多个平行，基本上不透明的间隔开的线，在第一和第二多条线之间具有相对小的角度。 当半导体本体上的第一多个的线的图像被设置在半导体本体上时，当监视器朝向和远离半导体主体相对运动时，线图像相对于半导体本体移动。 如果监视器朝向和离开半导体主体，则设置在半导体主体上的第二多个的线的图像在相对移动时以不同的方式移动。从第一和第二多个图像的图像形成在半导体主体上的莫尔条纹 分析这种移动期间的线，以便在半导体本体上实现图像的适当聚焦。

公开(公告)号：US06710853B1

公开(公告)日：2004-03-23

申请号：US09944795

申请日：2001-08-31

申请人： Bruno La Fontaine ,  Jongwook Kye ,  Harry Levinson

发明人： Bruno La Fontaine ,  Jongwook Kye ,  Harry Levinson

IPC分类号： G03B2752

CPC分类号： G03F7/70633 ,  G03F7/70641

摘要： An optical tool includes a tool body that is transparent to light. Pluralities of parallel opaque lines on the body form a first outline in the shape of the square, and a second outline in the shape of a square which is centrally located relative to and within the first-mentioned square. Each pair of adjacent parallel lines has therebetween a first region that allows transmission of light therethrough without changing phase thereof, and a second region alongside the first region that allows transmission of light therethrough while shifting the phase thereof by 90°. The phase shifting and non-phase shifting regions are positioned so that the images of the outlines provided by a lens on an object shit in position a substantial amount as the distance between the lens and the object is changed.

摘要翻译： 光学工具包括对光透明的工具主体。 身体上多条平行的不透明线条形成了正方形形状的第一轮廓，并且以相对于第一个提及的正方形中心定位的正方形形状的第二轮廓。 每对相邻的平行线之间具有允许透过其而不改变其相位的第一区域，以及沿着第一区域的第二区域，其允许透过光而使其相位偏移90°。 定位相移和非相移区域，使得当物体上的透镜提供的轮廓的图像在透镜和物体之间的距离改变时大量地位置处于位置。

公开(公告)号：US06399401B1

公开(公告)日：2002-06-04

申请号：US09912186

申请日：2001-07-24

申请人： Jongwook Kye ,  Harry Levinson

发明人： Jongwook Kye ,  Harry Levinson

IPC分类号： G01R3126

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  Y10S977/88 ,  Y10S977/887 ,  H01L2924/00

摘要： In a method of determining a linewidth of a polysilicon line formed by a lithographic process, a polysilicon layer is formed on a substrate. A line is patterned from said polysilicon layer using said lithographic process and a Van der Pauw structure is patterned from said polysilicon layer. N2 is then implanted into the polysilicon line and the polysilicon Van der Pauw structure to form a depletion barrier. A P-type dopant is the implanted into the polysilicon line and the polysilicon Van der Pauw structure and the dopant is activated. A sheet resistivity of the Van der Pauw structure is determined, and the linewidth of the polysilicon line is then determined by electrical linewidth measurement using the sheet resistivity of the Van der Pauw structure as the sheet resistivity of the polysilicon line. A related test structure is also disclosed.

摘要翻译： 在确定通过光刻工艺形成的多晶硅线的线宽的方法中，在衬底上形成多晶硅层。 使用所述光刻工艺从所述多晶硅层图案化线，并且从所述多晶硅层构图范德波瓦结构。 然后将N 2注入到多晶硅线和多晶硅Van der Pauw结构中以形成耗尽势垒。 P型掺杂剂被注入到多晶硅线中，并且多晶硅Van der Pauw结构和掺杂剂被激活。 确定Van der Pauw结构的薄层电阻率，然后通过使用Van der Pauw结构的薄层电阻率作为多晶硅线的薄层电阻率的电线宽测量来确定多晶硅线的线宽。 还公开了相关的测试结构。

公开(公告)号：US06696847B1

公开(公告)日：2004-02-24

申请号：US09907311

申请日：2001-07-17

申请人： Bruno M. LaFontaine ,  Jongwook Kye ,  Harry Levinson

发明人： Bruno M. LaFontaine ,  Jongwook Kye ,  Harry Levinson

IPC分类号： G01R31302

CPC分类号： G01R1/24 ,  G01R31/024

摘要： In the present method of electrically testing the width of a line, a short pulse of laser energy is applied to the line to generate conductive electrons therein. An electrical potential is applied to the line to cause electrons to flow in the line, and current is measured to determine the width of the line.

摘要翻译： 在电测试线的宽度的本方法中，将短脉冲的激光能量施加到线以在其中产生导电电子。 对线路施加电势以使电子在线路中流动，并且测量电流以确定线路的宽度。

公开(公告)号：US08741763B2

公开(公告)日：2014-06-03

申请号：US13465129

申请日：2012-05-07

申请人： Yuansheng Ma ,  Jongwook Kye ,  Harry Levinson ,  Hidekazu Yoshida ,  Mahbub Rashed

发明人： Yuansheng Ma ,  Jongwook Kye ,  Harry Levinson ,  Hidekazu Yoshida ,  Mahbub Rashed

IPC分类号： H01L21/44 ,  H01L23/528

CPC分类号： H01L21/76895 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11875 ,  H01L2924/0002 ,  H01L2924/00

摘要： An approach for providing layout designs with via routing structures is disclosed. Embodiments include: providing a gate structure and a diffusion contact on a substrate; providing a gate contact on the gate structure; providing a metal routing structure that does not overlie a portion of the gate contact, the diffusion contact, or a combination thereof; and providing a via routing structure over the portion and under a part of the metal routing structure to couple the gate contact, the diffusion contact, or a combination thereof to the metal routing structure.

摘要翻译： 公开了一种通过路由结构提供布局设计的方法。 实施例包括：在衬底上提供栅极结构和扩散接触; 在栅极结构上提供栅极接触; 提供不覆盖栅极接触部分，扩散接触部分或其组合的金属布线结构; 以及在金属布线结构的部分和一部分之下提供通孔布线结构以将栅极接触，扩散接触或其组合耦合到金属布线结构。

公开(公告)号：US08889561B2

公开(公告)日：2014-11-18

申请号：US13709541

申请日：2012-12-10

申请人： Youngtag Woo ,  Jongwook Kye ,  Dinesh Somasekhar

发明人： Youngtag Woo ,  Jongwook Kye ,  Dinesh Somasekhar

IPC分类号： H01L21/308 ,  H01L21/8238 ,  H01L27/11 ,  H01L27/088

CPC分类号： H01L27/1108 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/11

摘要： Methodology enabling a generation of fins having a variable fin pitch less than 40 nm, and the resulting device are disclosed. Embodiments include: forming a hardmask on a substrate; providing first and second mandrels on the hardmask; providing a first spacer on each side of each of the first and second mandrels; removing the first and second mandrels; providing, after removal of the first and second mandrels, a second spacer on each side of each of the first spacers; and removing the first spacers.

摘要翻译： 公开了能够产生具有可变翅片间距小于40nm的翅片的方法，并且所得到的装置被公开。 实施例包括：在基板上形成硬掩模; 在硬掩模上提供第一和第二心轴; 在每个第一和第二心轴的每一侧上提供第一间隔件; 去除第一和第二心轴; 在移除所述第一和第二心轴之后，在每个所述第一间隔件的每一侧上提供第二间隔件; 并移除第一间隔物。

公开(公告)号：US20140159164A1

公开(公告)日：2014-06-12

申请号：US13709541

申请日：2012-12-10

申请人： Youngtag WOO ,  Jongwook Kye ,  Dinesh Somasekhar

发明人： Youngtag WOO ,  Jongwook Kye ,  Dinesh Somasekhar

IPC分类号： H01L21/308 ,  H01L27/088

CPC分类号： H01L27/1108 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/11

摘要： Methodology enabling a generation of fins having a variable fin pitch less than 40 nm, and the resulting device are disclosed. Embodiments include: forming a hardmask on a substrate; providing first and second mandrels on the hardmask; providing a first spacer on each side of each of the first and second mandrels; removing the first and second mandrels; providing, after removal of the first and second mandrels, a second spacer on each side of each of the first spacers; and removing the first spacers.

公开(公告)号：US20140068543A1

公开(公告)日：2014-03-06

申请号：US13603304

申请日：2012-09-04

申请人： Lei Yuan ,  Jongwook Kye

发明人： Lei Yuan ,  Jongwook Kye

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5077

摘要： A method for enabling jogging functionality in circuit designs utilizing DPT without the need for difficult to implement tools such as stitch-aware routing tools is disclosed. Embodiments include: displaying a user interface for generating an IC having a plurality of masks for a single layer; causing, at least in part, a presentation in the user interface of a cell placement of the IC that includes a filler cell; and designating a portion of the filler cell as a routing zone, the routing zone being configured such that routes placed in the routing zone are decomposable with other routes placed outside the filler cell.

摘要翻译： 公开了一种使用DPT实现电路设计中的点动功能的方法，而不需要难以实现诸如针迹感知路由工具的工具。 实施例包括：显示用于生成具有用于单层的多个掩模的IC的用户界面; 至少部分地使得包括填充单元的IC的单元放置的用户界面中的呈现; 并且将所述填充单元的一部分指定为路由区域，所述路由区域被配置为使得放置在所述路由区域中的路由可以与放置在所述填充单元之外的其他路由分解。

公开(公告)号：US20130298089A1

公开(公告)日：2013-11-07

申请号：US13465909

申请日：2012-05-07

申请人： Lei Yuan ,  Hidekazu Yoshida ,  Youngtag Woo ,  Jongwook Kye

发明人： Lei Yuan ,  Hidekazu Yoshida ,  Youngtag Woo ,  Jongwook Kye

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F2217/12 ,  Y02P90/265

摘要： A method for increasing the robustness of a double patterning router used in the manufacture of integrated circuit devices that includes providing a set of original color rules defining an original color rule space, providing a set of integrated circuit designs defining a design space, providing a router processing engine, perturbing the original color rules to define a perturbed color rule space, applying the perturbed color rule space and the design space to the router processing engine to expose double pattern routing odd cycle decomposition errors, and feeding back the exposed decomposition errors to enhance router processing engine development by reconfiguring the router processing engine in accordance with the exposed decomposition errors.

摘要翻译： 一种用于增加用于制造集成电路器件的双重图案化路由器的鲁棒性的方法，其包括提供定义原始颜色规则空间的一组原始颜色规则，提供定义设计空间的一组集成电路设计，提供路由器 处理引擎，扰乱原始颜色规则以定义扰动的颜色规则空间，将扰动的颜色规则空间和设计空间应用于路由器处理引擎以暴露双模式路由奇数周期分解错误，并反馈暴露的分解错误以增强 通过根据暴露的分解错误重新配置路由器处理引擎来开发路由器处理引擎。

公开(公告)号：US20130295756A1

公开(公告)日：2013-11-07

申请号：US13465633

申请日：2012-05-07

申请人： Lei Yuan ,  Jin Cho ,  Jongwook Kye ,  Harry J. Levinson

发明人： Lei Yuan ,  Jin Cho ,  Jongwook Kye ,  Harry J. Levinson

IPC分类号： H01L21/28 ,  H01L21/283

CPC分类号： H01L21/823475 ,  H01L21/76895 ,  H01L23/485 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

摘要： One method disclosed herein includes forming a plurality of source/drain contacts that are conductively coupled to a source/drain region of a plurality of transistor devices, wherein at least one of the source/drain contacts is a local interconnect structure that spans the isolation region and is conductively coupled to a first source/drain region in a first active region and to a second source/drain region in a second active region, and forming a patterned mask layer that covers the first and second active regions and exposes at least a portion of the local interconnect structure positioned above an isolation region that separates the first and second active regions. The method further includes performing an etching process through the patterned mask layer to remove a portion of the local interconnect structure, thereby defining a recess positioned above a remaining portion of the local interconnect structure, and forming an insulating material in the recess.

摘要翻译： 本文公开的一种方法包括形成导电耦合到多个晶体管器件的源极/漏极区域的多个源极/漏极接触，其中源极/漏极接触中的至少一个是跨越隔离区域的局部互连结构 并且导电地耦合到第一有源区域中的第一源极/漏极区域和第二有源区域中的第二源极/漏极区域，并且形成覆盖第一和第二有源区域并且暴露至少一部分的图案化掩模层 的局部互连结构位于分离第一和第二有源区域的隔离区域之上。 该方法还包括通过图案化掩模层执行蚀刻工艺以移除局部互连结构的一部分，从而限定位于局部互连结构的剩余部分上方的凹槽，以及在凹部中形成绝缘材料。