利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

22 条记录 (耗时 0.027 秒)

    Data transmission and storage
    2.
    发明授权
    Data transmission and storage 失效
    数据传输和存储

    公开(公告)号：US5038374A

    公开(公告)日：1991-08-06

    申请号：US462403

    申请日：1990-01-08

    申请人： Malcolm E. A. Kaufman ,  Gerald P. Selden ,  Roger Booth ,  James C. Wickstead ,  Peter D. Ellis

    发明人： Malcolm E. A. Kaufman ,  Gerald P. Selden ,  Roger Booth ,  James C. Wickstead ,  Peter D. Ellis

    IPC分类号： H04M11/06

    CPC分类号： H04M11/06

    摘要： A sequence of data groups are modulated at a central location and coupled to a telephone line in response to a call-up signal. The sequence is transmitted through the telephone lines to a remote computer. The computer receives the signals, demodulates them, and couples them to a moemory. The data is stored at a particular address, and in coupling the data to the memory, the computer checks a flag at that address to determine whether the data has already been written over. When the flags indicate that the data received corresponds to data already written over, it signals the end of a transmission. The data stored in the memory can be accessed by an operator using input controls.

    摘要翻译： 数据组的序列在中央位置被调制并且响应于呼叫信号耦合到电话线路。 该序列通过电话线传输到远程计算机。 计算机接收信号，解调它们，并将它们耦合到一个动画。 数据存储在特定地址处，并且在将数据耦合到存储器时，计算机检查该地址处的标志，以确定数据是否已被写入。 当标志指示接收到的数据对应于已经写过的数据时，它表示发送的结束。 存储在存储器中的数据可由操作员使用输入控件访问。

    E-FUSE AND METHOD FOR FABRICATING E-FUSES INTEGRATING POLYSILICON RESISTOR MASKS
    5.
    发明申请
    E-FUSE AND METHOD FOR FABRICATING E-FUSES INTEGRATING POLYSILICON RESISTOR MASKS 审中-公开
    电子熔丝和电子熔模聚合多晶硅电阻掩模的方法

    公开(公告)号：US20070262413A1

    公开(公告)日：2007-11-15

    申请号：US11382808

    申请日：2006-05-11

    申请人： Roger Booth ,  William Hovis ,  Jack Mandelman ,  William Tonti

    发明人： Roger Booth ,  William Hovis ,  Jack Mandelman ,  William Tonti

    IPC分类号： H01L29/00

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An E-fuse and a method for fabricating an E-fuse are provided integrating polysilicon resistor masks. The E-fuse includes a polysilicon layer defining a fuse shape including a cathode, an anode, and a fuse neck connected between the cathode and the anode silicide formation. A silicide formation is formed on the polysilicon layer with an unsilicided portion extending over a portion of the cathode adjacent the fuse neck. The unsilicided portion substantially prevents current flow in the silicide formation region of the cathode, with electromigration occurring in the fuse neck during fuse programming. The unsilicided portion has a substantially lower series resistance than the series resistance of the fuse neck.

    摘要翻译： 集成了多晶硅电阻掩模的电子熔丝和用于制造电熔丝的方法被提供。 电熔丝包括限定熔丝形状的多晶硅层，其包括阴极，阳极和连接在阴极和阳极硅化物层之间的保险丝颈。 硅化物形成在多晶硅层上形成，其中非硅化部分在靠近熔丝颈部的阴极的一部分上延伸。 非接触部分基本上防止电流在阴极的硅化物形成区域中流动，在保险丝编程期间在保险丝颈部发生电迁移。 非接触部分具有比熔丝颈部的串联电阻显着更低的串联电阻。

    Electrically programmable fuse structures with narrowed width regions configured to enhance current crowding and methods of fabrication thereof
    6.
    发明申请
    Electrically programmable fuse structures with narrowed width regions configured to enhance current crowding and methods of fabrication thereof 有权
    具有变宽的宽度区域的电可编程熔丝结构被配置为增强电流拥挤及其制造方法

    公开(公告)号：US20070210413A1

    公开(公告)日：2007-09-13

    申请号：US11372386

    申请日：2006-03-09

    申请人： Roger Booth ,  Jack Mandelman ,  William Tonti

    发明人： Roger Booth ,  Jack Mandelman ,  William Tonti

    IPC分类号： H01L29/00

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Electrically programmable fuse structures and methods of fabrication thereof are presented, wherein a fuse includes first and second terminal portions interconnected by an elongate fuse element. The first terminal portion has a maximum width greater than a maximum width of the fuse element, and the fuse includes a narrowed width region where the first terminal portion and fuse element interface. The narrowed width region extends at least partially into and includes part of the first terminal portion. The width of the first terminal portion in the narrowed region is less than the maximum width of the first terminal portion to enhance current crowding therein. In another implementation, the fuse element includes a restricted width region wherein width of the fuse element is less than the maximum width thereof to enhance current crowding therein, and length of the restricted width region is less than a total length of the fuse element.

    摘要翻译： 提出了电可编程熔丝结构及其制造方法，其中熔丝包括通过细长的熔丝元件互连的第一和第二端部。 第一端子部分具有大于熔丝元件的最大宽度的最大宽度，并且熔丝包括第一端子部分和熔丝元件接合的变窄的宽度区域。 狭窄宽度区域至少部分地延伸并包括第一端子部分的一部分。 变窄区域中的第一端子部分的宽度小于第一端子部分的最大宽度，以增强其中的电流拥挤。 在另一实施方式中，熔丝元件包括限制宽度区域，其中熔丝元件的宽度小于其最大宽度以增强其中的电流拥挤，并且受限宽度区域的长度小于熔丝元件的总长度。

    Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures
    8.
    发明申请
    Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures 有权
    将镶嵌体FinFET和平面器件集成在共同衬底上的半导体结构以及用于形成这种半导体结构的方法

    公开(公告)号：US20070045748A1

    公开(公告)日：2007-03-01

    申请号：US11211956

    申请日：2005-08-25

    申请人： Roger Booth ,  Jack Mandelman ,  William Tonti

    发明人： Roger Booth ,  Jack Mandelman ,  William Tonti

    IPC分类号： H01L29/76

    CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/82385 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

    摘要： Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be interrupted to implant ions that are subsequently transformed into a region that electrically isolates the fin from the substrate. The isolation region is self-aligned with the fin because the mask used to form the damascene-body fin also serves as an implantation mask for the implanted ions. The fin may be supported by the patterned layer during processing that forms the FinFET and, more specifically, the gate of the FinFET. The electrical isolation surrounding the FinFET may also be supplied by a self-aligned process that recesses the substrate about the FinFET and at least partially fills the recess with a dielectric material.

    摘要翻译： 通过大马士革方法在公共基板上形成具有FinFET和诸如MOSFET的平面器件的半导体结构的方法。 FinFET的半导体鳍形成在具有镶嵌处理的衬底上，其中翅片生长可以被中断以注入离子，随后将其转换成将鳍片与衬底电隔离的区域。 隔离区域与翅片自对准，因为用于形成镶嵌体体翅片的掩模也用作注入离子的注入掩模。 翅片可以在形成FinFET的处理期间由图案化层支撑，更具体地，FinFET的栅极支撑。 围绕FinFET的电隔离也可以通过自对准工艺来提供，该工艺使得衬底围绕FinFET凹陷，并且用电介质材料至少部分地填充凹部。

    SEMICONDUCTOR STRUCTURES INTEGRATING DAMASCENE-BODY FINFET'S AND PLANAR DEVICES ON A COMMON SUBSTRATE AND METHODS FOR FORMING SUCH SEMICONDUCTOR STRUCTURES
    9.
    发明申请
    SEMICONDUCTOR STRUCTURES INTEGRATING DAMASCENE-BODY FINFET'S AND PLANAR DEVICES ON A COMMON SUBSTRATE AND METHODS FOR FORMING SUCH SEMICONDUCTOR STRUCTURES 有权
    在公共基板上集成大面积金属体和平面器件的半导体结构及其形成这样的半导体结构的方法

    公开(公告)号：US20080050866A1

    公开(公告)日：2008-02-28

    申请号：US11927780

    申请日：2007-10-30

    申请人： Roger Booth ,  Jack Mandelman ,  William Tonti

    发明人： Roger Booth ,  Jack Mandelman ,  William Tonti

    IPC分类号： H01L21/336

    CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/82385 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

    摘要： Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach, and semiconductor structures formed by the methods. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be interrupted to implant ions that are subsequently transformed into a region that electrically isolates the fin from the substrate. The isolation region is self-aligned with the fin because the mask used to form the damascene-body fin also serves as an implantation mask for the implanted ions. The fin may be supported by the patterned layer during processing that forms the FinFET and, more specifically, the gate of the FinFET. The electrical isolation surrounding the FinFET may also be supplied by a self-aligned process that recesses the substrate about the FinFET and at least partially fills the recess with a dielectric material.

    摘要翻译： 通过镶嵌法在公共衬底上形成具有FinFET和诸如MOSFET的平面器件的半导体结构的方法以及通过该方法形成的半导体结构。 FinFET的半导体鳍形成在具有镶嵌处理的衬底上，其中翅片生长可以被中断以注入离子，随后将其转换成将鳍片与衬底电隔离的区域。 隔离区域与翅片自对准，因为用于形成镶嵌体体翅片的掩模也用作注入离子的注入掩模。 翅片可以在形成FinFET的处理期间由图案化层支撑，更具体地，FinFET的栅极支撑。 围绕FinFET的电隔离也可以通过自对准工艺来提供，该工艺使得衬底围绕FinFET凹陷，并且用电介质材料至少部分地填充凹部。

    E-Fuse and Method for Fabricating E-Fuses Integrating Polysilicon Resistor Masks
    10.
    发明申请
    E-Fuse and Method for Fabricating E-Fuses Integrating Polysilicon Resistor Masks 审中-公开
    电子保险丝和电子熔丝的制造方法，集成多晶硅电阻掩模

    公开(公告)号：US20080029843A1

    公开(公告)日：2008-02-07

    申请号：US11873197

    申请日：2007-10-16

    申请人： Roger Booth ,  William Hovis ,  Jack Mandelman ,  William Tonti

    发明人： Roger Booth ,  William Hovis ,  Jack Mandelman ,  William Tonti

    IPC分类号： H01L29/41

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An E-fuse and a method for fabricating an E-fuse integrating polysilicon resistor masks, and a design structure on which the subject E-fuse circuit resides are provided. The E-fuse includes a polysilicon layer defining a fuse shape including a cathode, an anode, and a fuse neck connected between the cathode and the anode silicide formation. A silicide formation is formed on the polysilicon layer with an unsilicided portion extending over a portion of the cathode adjacent the fuse neck. The unsilicided portion substantially prevents current flow in the silicide formation region of the cathode, with electromigration occurring in the fuse neck during fuse programming. The unsilicided portion has a substantially lower series resistance than the series resistance of the fuse neck.

    摘要翻译： 一种电熔丝和一种用于制造集成多晶硅电阻掩模的电子熔丝的方法，以及设置有被检体E熔丝回路的设计结构。 电熔丝包括限定熔丝形状的多晶硅层，其包括阴极，阳极和连接在阴极和阳极硅化物层之间的保险丝颈。 硅化物形成在多晶硅层上形成，其中非硅化部分在靠近熔丝颈部的阴极的一部分上延伸。 非接触部分基本上防止电流在阴极的硅化物形成区域中流动，在保险丝编程期间在保险丝颈部发生电迁移。 非接触部分具有比熔丝颈部的串联电阻显着更低的串联电阻。