公开(公告)号：US09577115B2

公开(公告)日：2017-02-21

申请号：US13195347

申请日：2011-08-01

申请人： Byung-Kyu Cho ,  Chang-Hyun Lee ,  Young-Woo Park

发明人： Byung-Kyu Cho ,  Chang-Hyun Lee ,  Young-Woo Park

IPC分类号： H01L21/70 ,  H01L29/788 ,  H01L21/764 ,  H01L27/115 ,  H01L29/423

CPC分类号： H01L29/7881 ,  H01L21/764 ,  H01L27/11521 ,  H01L29/42336

摘要： A semiconductor device has an isolation layer pattern, a plurality of gate structures, and a first insulation layer pattern. The isolation layer pattern is formed on a substrate and has a recess thereon. The gate structures are spaced apart from each other on the substrate and the isolation layer pattern. The first insulation layer pattern is formed on the substrate and covers the gate structures and an inner wall of the recess. The first insulation layer pattern has a first air gap therein.

摘要翻译： 半导体器件具有隔离层图案，多个栅极结构和第一绝缘层图案。 隔离层图案形成在基板上并且在其上具有凹部。 栅极结构在衬底和隔离层图案上彼此间隔开。 第一绝缘层图案形成在基板上并且覆盖该凹槽的栅极结构和内壁。 第一绝缘层图案中具有第一气隙。

公开(公告)号：US20120037975A1

公开(公告)日：2012-02-16

申请号：US13195347

申请日：2011-08-01

申请人： Byung-Kyu CHO ,  Chang-Hyun Lee ,  Young-Woo Park

发明人： Byung-Kyu CHO ,  Chang-Hyun Lee ,  Young-Woo Park

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  H01L21/764 ,  H01L27/11521 ,  H01L29/42336

摘要： A semiconductor device has an isolation layer pattern, a plurality of gate structures, and a first insulation layer pattern. The isolation layer pattern is formed on a substrate and has a recess thereon. The gate structures are spaced apart from each other on the substrate and the isolation layer pattern. The first insulation layer pattern is formed on the substrate and covers the gate structures and an inner wall of the recess. The first insulation layer pattern has a first air gap therein.

摘要翻译： 半导体器件具有隔离层图案，多个栅极结构和第一绝缘层图案。 隔离层图案形成在基板上并且在其上具有凹部。 栅极结构在衬底和隔离层图案上彼此间隔开。 第一绝缘层图案形成在基板上并且覆盖该凹槽的栅极结构和内壁。 第一绝缘层图案中具有第一气隙。

公开(公告)号：US20090212340A1

公开(公告)日：2009-08-27

申请号：US12392656

申请日：2009-02-25

申请人： Chang-Hyun Lee ,  Young-Woo Park ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Jin-Taek Park

发明人： Chang-Hyun Lee ,  Young-Woo Park ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Jin-Taek Park

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  H01L27/11521

摘要： A gate electrode line which extends in a second direction crossing a first direction on a substrate including an active region which is defined by a device isolation layer and extends in the first direction and a charge trap layer disposed between the active region and the gate electrode line, wherein a bottom surface of the gate electrode line disposed on the device isolation layer is lower than a top surface of the charge trap layer disposed on the active region and higher than a top surface of the active region.

摘要翻译： 一种栅极电极线，其在包括由器件隔离层限定并在第一方向上延伸的有源区域和设置在有源区域和栅电极线之间的电荷陷阱层的基板上沿与第一方向交叉的第二方向延伸 其特征在于，设置在所述器件隔离层上的所述栅电极线的底面低于设置在所述有源区上并高于所述有源区的顶面的所述电荷陷阱层的顶面。

公开(公告)号：US20120146118A1

公开(公告)日：2012-06-14

申请号：US13248333

申请日：2011-09-29

申请人： Chang-Hyun Lee ,  Young-Woo Park ,  Kye-Hyun Kyung ,  Cheon-An Lee ,  Sung-il Chang ,  Chul Bum Kim

发明人： Chang-Hyun Lee ,  Young-Woo Park ,  Kye-Hyun Kyung ,  Cheon-An Lee ,  Sung-il Chang ,  Chul Bum Kim

IPC分类号： H01L27/108 ,  H01L27/092

CPC分类号： H01L21/823857 ,  G11C16/0483 ,  G11C16/30 ,  H01L27/105 ,  H01L27/11546 ,  H01L27/11556

摘要： A semiconductor memory device has a memory cell region and a peripheral region. The device includes low voltage transistors at the peripheral region having gate insulation films with different thicknesses. For example, a gate insulation film of a low voltage transistor used in an input/output circuit of the memory device may be thinner than the gate insulation film of a low voltage transistor used in a core circuit for the memory device. Since low voltage transistors used at an input/output circuit are formed to be different from low voltage transistors used at a core circuit or a high voltage pump circuit, high speed operation and low power consumption characteristics of a non-volatile memory device may be.

摘要翻译： 半导体存储器件具有存储单元区域和周边区域。 该器件包括具有不同厚度的栅极绝缘膜的外围区域的低电压晶体管。 例如，在存储器件的输入/输出电路中使用的低电压晶体管的栅极绝缘膜可以比用于存储器件的核心电路中的低电压晶体管的栅极绝缘膜更薄。 由于在输入/输出电路中使用的低压晶体管形成为与核心电路或高压泵浦电路所使用的低压晶体管不同，所以可以是非易失性存储器件的高速工作和低功耗特性。

公开(公告)号：US09324727B2

公开(公告)日：2016-04-26

申请号：US14176332

申请日：2014-02-10

申请人： Chang-Hyun Lee ,  Hyun-Jung Kim ,  Dong-Hoon Jang ,  Albert Fayrushin

发明人： Chang-Hyun Lee ,  Hyun-Jung Kim ,  Dong-Hoon Jang ,  Albert Fayrushin

IPC分类号： H01L27/115 ,  H01L21/762 ,  H01L23/48 ,  H01L29/788

CPC分类号： H01L27/11582 ,  H01L21/76224 ,  H01L27/11551 ,  H01L27/11565 ,  H01L29/7889

摘要： A memory device may include a plurality of semiconductor patterns on a substrate including a plurality of first impurity regions doped at a first impurity concentration, a plurality of second impurity regions at portions of the substrate contacting the plurality of semiconductor patterns and doped at a second impurity concentration, a plurality of channel patterns on the plurality of semiconductor patterns, a plurality of gate structures, a plurality of third impurity regions at portions of the substrate adjacent to end portions of the plurality of gate structures, and a plurality of fourth impurity regions at portions of the substrate between the second and third impurity regions and between adjacent second impurity regions. The plurality of fourth impurity regions may be doped at a third impurity concentration which may be lower than the first and second impurity concentrations.

摘要翻译： 存储器件可以包括在衬底上的多个半导体图案，其包括以第一杂质浓度掺杂的多个第一杂质区域，在与多个半导体图案接触并且以第二杂质掺杂的衬底的部分处的多个第二杂质区域 浓度，多个半导体图案上的多个沟道图案，多个栅极结构，在与多个栅极结构的端部相邻的基板的部分处的多个第三杂质区域，以及多个第四杂质区域 在第二和第三杂质区之间和相邻的第二杂质区之间的衬底的部分。 可以在可以低于第一和第二杂质浓度的第三杂质浓度下掺杂多个第四杂质区域。

公开(公告)号：US08629489B2

公开(公告)日：2014-01-14

申请号：US13357350

申请日：2012-01-24

申请人： Chang-Hyun Lee ,  Jung-Dal Choi

发明人： Chang-Hyun Lee ,  Jung-Dal Choi

IPC分类号： H01L29/76

CPC分类号： H01L27/1052 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524

摘要： A nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. First impurity layers are formed at boundaries of the channels and the source/drain regions of the memory cell transistors. The first impurity layers are doped with opposite conductivity type impurities relative to the source/drain regions of the memory cell transistors. Second impurity layers are formed at boundaries between a channel and a drain region of the string selection transistor and between a channel and a source region of the ground selection transistor. The second impurity layers are doped with the same conductivity type impurities as the first impurity layers and have a higher impurity concentration than the first impurity layers.

摘要翻译： 非易失性存储器件包括串选择晶体管，多个存储单元晶体管和与串选择晶体管和多个存储单元晶体管串联电连接的接地选择晶体管。 在存储单元晶体管的沟道和源极/漏极区的边界处形成第一杂质层。 相对于存储单元晶体管的源/漏区，第一杂质层掺杂有相反导电类型的杂质。 第二杂质层形成在串选择晶体管的沟道和漏极区之间的边界处，并且在地选择晶体管的沟道和源极区之间形成。 第二杂质层掺杂有与第一杂质层相同的导电类型杂质，并且具有比第一杂质层更高的杂质浓度。

公开(公告)号：US08324052B2

公开(公告)日：2012-12-04

申请号：US13010583

申请日：2011-01-20

申请人： Dong-Yean Oh ,  Jai-Hyuk Song ,  Chang-Sub Lee ,  Chang-Hyun Lee ,  Hyun-Jae Kim

发明人： Dong-Yean Oh ,  Jai-Hyuk Song ,  Chang-Sub Lee ,  Chang-Hyun Lee ,  Hyun-Jae Kim

IPC分类号： H01L21/331

CPC分类号： H01L27/11521 ,  H01L21/26586 ,  H01L27/115 ,  H01L27/11524

摘要： A nonvolatile memory device includes a string selection gate and a ground selection gate on a semiconductor substrate, and a plurality of memory cell gates on the substrate between the string selection gate and the ground selection gate. First impurity regions extend into the substrate to a first depth between ones of the plurality of memory cell gates. Second impurity regions extend into the substrate to a second depth that is greater than the first depth between the string selection gate and a first one of the plurality of memory cell gates immediately adjacent thereto, and between the ground selection gate and a last one of the plurality of memory cell gates immediately adjacent thereto. Related fabrication methods are also discussed.

摘要翻译： 非易失性存储器件包括半导体衬底上的串选择栅极和接地选择栅极，以及在串选择栅极和地选择栅极之间的衬底上的多个存储单元栅极。 第一杂质区域延伸到衬底中到多个存储单元门之间的第一深度。 第二杂质区域延伸到衬底中的第二深度，该第二深度大于串选择栅极与紧邻其之间的多个存储单元栅极中的第一深度之间以及在接地选择栅极和最后一个栅极选择栅极之间的第一深度 与其紧邻的多个存储单元门。 还讨论了相关的制造方法。

公开(公告)号：US20110111570A1

公开(公告)日：2011-05-12

申请号：US13010583

申请日：2011-01-20

申请人： Dong-Yean Oh ,  Jai-Hyuk Song ,  Chang-Sub Lee ,  Chang-Hyun Lee ,  Hyun-Jae Kim

发明人： Dong-Yean Oh ,  Jai-Hyuk Song ,  Chang-Sub Lee ,  Chang-Hyun Lee ,  Hyun-Jae Kim

IPC分类号： H01L21/8234

CPC分类号： H01L27/11521 ,  H01L21/26586 ,  H01L27/115 ,  H01L27/11524

摘要： A nonvolatile memory device includes a string selection gate and a ground selection gate on a semiconductor substrate, and a plurality of memory cell gates on the substrate between the string selection gate and the ground selection gate. First impurity regions extend into the substrate to a first depth between ones of the plurality of memory cell gates. Second impurity regions extend into the substrate to a second depth that is greater than the first depth between the string selection gate and a first one of the plurality of memory cell gates immediately adjacent thereto, and between the ground selection gate and a last one of the plurality of memory cell gates immediately adjacent thereto. Related fabrication methods are also discussed.

摘要翻译： 非易失性存储器件包括半导体衬底上的串选择栅极和接地选择栅极，以及在串选择栅极和地选择栅极之间的衬底上的多个存储单元栅极。 第一杂质区域延伸到衬底中到多个存储单元门之间的第一深度。 第二杂质区域延伸到衬底中的第二深度，该第二深度大于串选择栅极与紧邻其之间的多个存储单元栅极中的第一深度之间以及在接地选择栅极和最后一个栅极选择栅极之间的第一深度 与其紧邻的多个存储单元门。 还讨论了相关的制造方法。

公开(公告)号：US20110079838A1

公开(公告)日：2011-04-07

申请号：US12961678

申请日：2010-12-07

申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Jin-Taek Park ,  Byeong-In Choe

发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Jin-Taek Park ,  Byeong-In Choe

IPC分类号： H01L29/788 ,  H01L29/792

CPC分类号： H01L27/1157 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/42352 ,  H01L29/7851 ,  H01L29/792

摘要： A method of fabricating a semiconductor device includes forming a fin-shaped active region including opposing sidewalls and a surface therebetween protruding from a substrate, forming a gate structure on the surface of the active region, and performing an ion implantation process to form source/drain regions in the active region at opposite sides of the gate structure. The source/drain regions respectively include a first impurity region in the surface of the active region and second impurity regions in the opposing sidewalls of the active region. The first impurity region has a doping concentration that is greater than that of the second impurity regions. Related devices are also discussed.

摘要翻译： 一种制造半导体器件的方法包括：形成鳍状有源区，包括相对的侧壁和从衬底突出的表面，在有源区的表面上形成栅极结构，并执行离子注入工艺以形成源极/漏极 在栅极结构的相对侧的有源区中的区域。 源极/漏极区域分别包括有源区的表面中的第一杂质区域和有源区的相对侧壁中的第二杂质区。 第一杂质区域的掺杂浓度大于第二杂质区域的掺杂浓度。 还讨论了相关设备。

公开(公告)号：US20110045647A1

公开(公告)日：2011-02-24

申请号：US12916718

申请日：2010-11-01

申请人： Jin-Hwa Heo ,  Chul-Sung Kim ,  Bon-Young Koo ,  Ki-Hyun Hwang ,  Chang-Hyun Lee

发明人： Jin-Hwa Heo ,  Chul-Sung Kim ,  Bon-Young Koo ,  Ki-Hyun Hwang ,  Chang-Hyun Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  H01L21/28202 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/518

摘要： A non-volatile memory device includes a dielectric layer between a charge storage layer and a substrate. Free bonds of the dielectric layer can be reduced to reduce/prevent charges from leaking through the free bonds and/or from being trapped by the free bonds. As a result, data retention properties and/or durability of a non-volatile memory device may be enhanced.

摘要翻译： 非易失性存储器件包括电荷存储层和衬底之间的电介质层。 可以减少电介质层的自由键，以减少/防止电荷通过游离键泄漏和/或被游离键捕获。 结果，可以增强非挥发性存储器件的数据保持性能和/或耐久性。