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    IMAGE PROCESSING METHOD
    2.
    发明申请
    IMAGE PROCESSING METHOD 审中-公开

    公开(公告)号：US20190019307A1

    公开(公告)日：2019-01-17

    申请号：US16031085

    申请日：2018-07-10

    申请人： Commissariat a l'Energie Atomique et aux Energies Alternatives

    发明人： Camille DUPOIRON ,  William GUICQUERO ,  Gilles SICARD ,  Arnaud VERDANT

    IPC分类号： G06T7/73 ,  G06T7/90

    摘要： A method of processing an image including pixels distributed in cells and in blocks is disclosed, the method including the steps of: a) for each cell, generating n first intensity values of gradients having different orientations, each first value being a weighted sum of the values of the pixels of the cell; b) for each cell, determining a main gradient orientation of the cell and a second value representative of the intensity of the gradient in the main orientation; c) for each block, generating a descriptor of n values respectively corresponding, for each of the n gradient orientations, to the sum of the second values of the cells of the block having the gradient orientation considered as the main gradient orientation.

    MATRIX-ARRAY SENSOR WITH TEMPORAL CODING WITHOUT ARBITRATION
    6.
    发明申请
    MATRIX-ARRAY SENSOR WITH TEMPORAL CODING WITHOUT ARBITRATION 审中-公开

    公开(公告)号：US20180295308A1

    公开(公告)日：2018-10-11

    申请号：US15946653

    申请日：2018-04-05

    申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

    发明人： Camille DUPOIRON ,  Gilles SICARD ,  Arnaud VERDANT

    IPC分类号： H04N5/378 ,  H04N5/3745

    CPC分类号： H04N5/3355 ,  H04L1/12 ,  H04N5/3741 ,  H04N5/3745 ,  H04N5/378

    摘要： A matrix-array sensor comprises a matrix of detection elements arranged in rows and columns and a readout circuit for each column, the elements of one and the same column linked to the corresponding readout circuit via a bus, each element comprising a sensor, a charge integrator configured to accumulate charge generated by the sensor, a comparator configured to generate a trigger signal when a voltage level across the terminals of this comparator reaches a threshold level, and a bus access logic circuit which is configured to receive, as input, the trigger signal and to attempt to transmit, over the bus, an address of the element in the column, wherein the elements of one and the same column have predetermined bus access priority levels, and wherein the bus access logic circuit of each element is configured: to abandon transmission of the address and reset the charge integrator of the detection element if the bus is pre-empted by an element having a higher priority level; to count the number of attempts made before being able to transmit the address; and to communicate the number to the readout circuit along with the address of the element.

    COMPENSATED COMPARATOR
    8.
    发明申请
    COMPENSATED COMPARATOR 审中-公开

    公开(公告)号：US20190214977A1

    公开(公告)日：2019-07-11

    申请号：US16236723

    申请日：2018-12-31

    申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

    发明人： Arnaud VERDANT

    IPC分类号： H03K5/24 ,  H03K5/15

    CPC分类号： H03K5/2481 ,  H03K5/1506 ,  H03K19/01707 ,  H03K19/0966

    摘要： A compensated comparator is provided, including a decision stage and a differential stage provided with two transistors connected by their sources, the differential stage being provided with compensation means to compensate the effects of a dispersion of the threshold voltages of the transistors forming the differential stage, the compensation means including first and second capacitors each connected to a gate of one of the two transistors, and being configured to memorize a voltage that is a function of a threshold voltage of the considered transistors.