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公开(公告)号：US20240133686A1
公开(公告)日：2024-04-25
申请号：US17769598
申请日：2020-10-28
Applicant: CANON KABUSHIKI KAISHA
Inventor： Kohichi Nakamura , Masaki Sato , Daisuke Kobayashi , Tetsuya Itano , Daisuke Yoshida
IPC: G01C3/02 , H03K17/687 , H04L25/02 , H04N25/709
CPC classification number: G01C3/02 , H03K17/6871 , H04L25/0282 , H04N25/709 , H03F3/45475
Abstract: The disclosed apparatus includes a plurality of differential transmitters, and a power supply circuit that supplies a power supply voltage to each of the plurality of differential transmitters. The power supply circuit includes a common circuit unit that defines the power supply voltage supplied to the plurality of differential transmitters, and a plurality of individual circuit units provided in association with the plurality of differential transmitters and each connected to the common circuit unit. Each of the plurality of individual circuit units has an output node that outputs the power supply voltage defined by the common circuit unit to a corresponding differential transmitter of the plurality of differential transmitters, and respective output nodes of the plurality of individual circuit units are connected to each other.
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2.发明授权公开(公告)号：US11683610B2
公开(公告)日：2023-06-20
申请号：US17590895
申请日：2022-02-02
Applicant: CANON KABUSHIKI KAISHA
Inventor： Kazuhiro Saito , Kohichi Nakamura , Tetsuya Itano
Abstract: A photoelectric converter includes a pixel array including a plurality of pixels, a capacitive coupling amplifier configured to amplify a signal output from the pixel array, and a delta-sigma AD converter configured to convert, into a digital signal, an analog signal output from the amplifier. The amplifier is formed by a plurality of first elements including an active element and a capacitive element. The delta-sigma AD converter is formed by a plurality of second elements including an active element and a capacitive element. A breakdown voltage of at least one of the plurality of second elements forming the delta-sigma AD converter is lower than a breakdown voltage of the plurality of first elements forming the amplifier.
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公开(公告)号：US20220337230A1
公开(公告)日：2022-10-20
申请号：US17718350
申请日：2022-04-12
Applicant: CANON KABUSHIKI KAISHA
Inventor： Kohichi Nakamura , Yasuhiro Oguro
Abstract: Provided is a logic circuit including a first circuit including a static D flip-flop and a second circuit including a dynamic D flip-flop. The first circuit receives a clock signal and a first reset signal. The first circuit outputs a second reset signal generated by synchronizing the first reset signal with the clock signal. The second circuit receives the clock signal and a signal based on the second reset signal.
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公开(公告)号：US20220247958A1
公开(公告)日：2022-08-04
申请号：US17590887
申请日：2022-02-02
Applicant: CANON KABUSHIKI KAISHA
Inventor： Kohichi Nakamura
Abstract: A photoelectric converter includes a structure in which a first substrate and a second substrate are stacked, wherein a pixel array including a plurality of pixels is arranged on the first substrate, and at least part of a sample-and-hold circuit configured to sample and hold a signal output from the pixel array is arranged on the first substrate, and wherein at least part of a delta-sigma AD converter configured to convert an analog signal output from the sample-and-hold circuit into a digital signal is arranged on the second substrate.
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公开(公告)号：US11258973B2
公开(公告)日：2022-02-22
申请号：US17001323
申请日：2020-08-24
Applicant: CANON KABUSHIKI KAISHA
Inventor： Koichiro Iwata , Yoshiaki Takada , Kohichi Nakamura
IPC: H04N5/374 , H04N5/3745 , H03M1/56 , H04N5/376 , H04N5/378
Abstract: An AD conversion circuit includes a comparator configured to compare an analog signal with a ramp signal and output a comparison result signal indicating a result of the comparison, and performs an AD conversion using the comparison result signal. In the comparison, a potential of the ramp signal changes with a lapse of time from a first potential to a second potential. Before the comparison, the potential of the ramp signal changes at a first change rate and then changes at a second change rate smaller than the first change rate, the potential of the ramp signal changes from the first potential to a third potential between the first potential and the second potential, and the comparator is reset in a state where the third potential is input to the comparator.
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Patent Agency Ranking
公开(公告)号：US20200273901A1
公开(公告)日：2020-08-27
申请号：US16798929
申请日：2020-02-24
Applicant: CANON KABUSHIKI KAISHA
Inventor： Kohichi Nakamura , Yoshikazu Yamazaki
IPC: H01L27/146 , H01L23/00 , H01L49/02 , H01L23/522 , H04N5/3745 , H04N5/378
Abstract: A semiconductor apparatus of the present disclosure includes: a first semiconductor component in which a first circuit unit is provided; and a second semiconductor component in which a second circuit unit is provided and which is stacked to the first semiconductor component, and the second semiconductor component includes a capacitor unit as a decoupling capacitor having a first node and a second node that are connected to the first circuit unit.
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公开(公告)号：US20180219037A1
公开(公告)日：2018-08-02
申请号：US15936386
申请日：2018-03-26
Applicant: CANON KABUSHIKI KAISHA
Inventor： Kohichi Nakamura , Masaaki Iwane
IPC: H01L27/146 , H04N5/378
CPC classification number: H01L27/14612 , H01L27/14605 , H01L27/14609 , H04N5/378
Abstract: A solid-state imaging device includes a plurality of pixels, a reference signal supply unit configured to output a reference signal, and a comparison unit configured to output a signal depending on the reference signal and a signal from the pixel. The comparison unit includes a comparator circuit including an input terminal and an output terminal, a first switch configured to connect the input terminal and the output terminal of the comparator circuit, a clamp capacitor including a first terminal connected to the input terminal of the comparator circuit, a second switch connected to a second terminal of the clamp capacitor, and configured to select one of the signal from the pixel and the reference signal and to input the selected signal to the second terminal, and a clipping circuit arranged in an electrical path through which the reference signal is input to the comparator circuit.
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公开(公告)号：US09966398B2
公开(公告)日：2018-05-08
申请号：US15217537
申请日：2016-07-22
Applicant: CANON KABUSHIKI KAISHA
Inventor： Kohichi Nakamura , Masaaki Iwane
IPC: H04N5/335 , H03M1/12 , H01L27/146 , H04N5/378
CPC classification number: H01L27/14612 , H01L27/14605 , H01L27/14609 , H04N5/378
Abstract: A solid-state imaging device includes a plurality of pixels, a reference signal supply unit configured to output a reference signal, and a comparison unit configured to output a signal depending on the reference signal and a signal from the pixel. The comparison unit includes a comparator circuit including an input terminal and an output terminal, a first switch configured to connect the input terminal and the output terminal of the comparator circuit, a clamp capacitor including a first terminal connected to the input terminal of the comparator circuit, a second switch connected to a second terminal of the clamp capacitor, and configured to select one of the signal from the pixel and the reference signal and to input the selected signal to the second terminal, and a clipping circuit arranged in an electrical path through which the reference signal is input to the comparator circuit.
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公开(公告)号：US09602752B2
公开(公告)日：2017-03-21
申请号：US14591180
申请日：2015-01-07
Applicant: CANON KABUSHIKI KAISHA
Inventor： Hideo Kobayashi , Kohichi Nakamura , Tetsuya Itano , Yasushi Matsuno
IPC: H04N5/3745 , H04N5/378 , H01L27/146 , H03M1/12
CPC classification number: H04N5/378 , H01L27/14603 , H03M1/12 , H04N5/3745 , H04N5/37452 , H04N5/37455
Abstract: A solid-state imaging apparatus includes: a pixels in a matrix for generating a pixel signal; and A/D converting units, corresponding to columns of the matrix, to convert the pixel signal into a n-bit digital value. The A/D converting units includes first storage units for storing the n-bit digital value one bit by one bit, and second storage units corresponding to the first storage units, to hold the digital value transferred from the first storage unit. In each of the columns of the plurality of pixels, arranged corresponding thereto are the first storage units and the second storage units form n-pairs. Each pair including the first storage unit and the second storage unit hold the digital value of the same bit. The n-pairs are arrayed in a matrix.
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公开(公告)号：US09438828B2
公开(公告)日：2016-09-06
申请号：US14614980
申请日：2015-02-05
Applicant: CANON KABUSHIKI KAISHA
Inventor： Tetsuya Itano , Kohichi Nakamura , Hideo Kobayashi
IPC: H04N5/355 , H04N5/345 , H04N5/347 , H04N5/3745 , H04N101/00
CPC classification number: H04N5/35554 , H04N5/3456 , H04N5/3458 , H04N5/347 , H04N5/3745 , H04N9/04511 , H04N2101/00
Abstract: Provided is a photoelectric conversion apparatus including: a pixel array having pixels arranged in matrix; a pixel output line provided according to each column of the pixel array and transmitting a pixel signal output from a pixel of each column of the pixel array; a column signal processing unit provided according to each column of the pixel array and into which the pixel signal is input from the pixel output line, in which the column signal processing unit has a plurality of horizontal adding up or averaging units configured to add up or average the plurality of pixel signals based on the pixels of different columns of the pixel array; and a plurality of adding up or averaging modes with different numbers of columns subjected to adding up or averaging can be selected by selectively using one or a plurality of the plurality of horizontal adding up or averaging units.
Abstract translation: 提供一种光电转换装置，包括：具有以矩阵排列的像素的像素阵列; 根据像素阵列的每列提供的像素输出线，并且传输从像素阵列的每列的像素输出的像素信号; 列信号处理单元，根据像素阵列的每列提供，并且从像素输出线输入像素信号，其中列信号处理单元具有多个水平相加或平均单元，其被配置为相加或 基于像素阵列的不同列的像素来平均多个像素信号; 并且可以通过选择性地使用多个水平相加或平均单元中的一个或多个来选择具有经受相加或平均的不同列数的多个相加或平均模式。
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