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1.发明授权Method and circuit for suppressing data loading noise in nonvolatile memories 失效用于抑制非易失性存储器中的数据加载噪声的方法和电路
公开(公告)号：US5541884A
公开(公告)日：1996-07-30
申请号：US391147
申请日：1995-02-21
申请人： Luigi Pascucci , Carla M. Golla , Marco Maccarrone , Marco Olivo
发明人： Luigi Pascucci , Carla M. Golla , Marco Maccarrone , Marco Olivo
CPC分类号： G11C7/02 , G11C16/32 , G11C7/1006 , G11C7/22
摘要： In a nonvolatile memory comprising a data amplifying unit and an output element mutually connected by a connection line, the noise suppressing circuit comprises a network for generating a noise suppressing signal which is synchronized substantially perfectly with a signal controlling data loading from the amplifying unit to the output unit, presents a very short duration, equal to the switching time of the output unit, and freezes the amplifying unit during switching of the output unit to prevent this from altering the data stored in the amplifying unit or internal circuits of the memory. The same signal also blocks an address amplifying unit on the address bus.
摘要翻译： 在包括数据放大单元和通过连接线相互连接的输出元件的非易失性存储器中，噪声抑制电路包括用于产生噪声抑制信号的网络，该噪声抑制信号与控制从放大单元加载到 输出单元呈现相当于输出单元的切换时间的非常短的持续时间，并且在切换输出单元期间使放大单元冻结，以防止其改变存储在放大单元中的数据或存储器的内部电路。 相同的信号也阻塞地址总线上的地址放大单元。
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2.发明授权Double-row address decoding and selection circuitry for an electrically erasable and programmable non-volatile memory device with redundancy, particularly for flash EEPROM devices 失效双行地址解码和选择电路，用于具有冗余的电可擦除和可编程的非易失性存储器件，特别是用于闪存EEPROM器件
公开(公告)号：US5581509A
公开(公告)日：1996-12-03
申请号：US356740
申请日：1994-12-15
申请人： Carla M. Golla , Marco Olivo
发明人： Carla M. Golla , Marco Olivo
摘要： A double-row address decoding and selection circuitry for an electrically erasable and programmable non-volatile memory device with redundancy comprises a plurality of identical circuit blocks supplied with address signals and each one generating a respective selection signal which is activated by a particular logic configuration of said address signals for the selection of a particular row of the matrix; each one of said circuit blocks also generates a carry-out signal which is supplied to a carry-in input of a following circuit block and is activated when the respective selection signal is activated; a first circuit block of said plurality of circuit blocks has the respective carry-in input connected to a reference voltage; each of said circuit blocks is also supplied with a control signal, which is activated by a control circuitry of the memory device when, during a preprogramming operation preceding an electrical erasure of the memory device, a defective row is addressed, to enable the activation of the respective selection signal if the carry-out signal supplying the respective carry-in input is activated, so that two adjacent rows can be simultaneously selected.
摘要翻译： 用于具有冗余的电可擦除和可编程非易失性存储器件的双行地址解码和选择电路包括提供有地址信号的多个相同的电路块，并且每个电路块产生相应的选择信号，该选择信号由特定逻辑配置 所述地址信号用于选择矩阵的特定行; 所述电路块中的每一个还产生提供给后续电路块的进位输入的进位信号，并且当各个选择信号被激活时被激活; 所述多个电路块的第一电路块具有连接到参考电压的相应输入输入; 每个所述电路块还被提供有控制信号，该控制信号由存储器件的控制电路激活，当在存储器件的电擦除之前的预编程操作期间寻址有缺陷的行时，以使得能够激活 如果提供相应进位输入的进位信号被激活，则相应的选择信号被激活，使得可以同时选择两个相邻的行。
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公开(公告)号：US5627790A
公开(公告)日：1997-05-06
申请号：US408589
申请日：1995-03-22
申请人： Carla M. Golla , Marco Olivo , Silvia Padoan
发明人： Carla M. Golla , Marco Olivo , Silvia Padoan
摘要： A device including a load connected by a selection circuit to a number of bit lines, and a load connected to a reference cell, for detecting the current in the selected bit line and in the reference cell. The load connected to the bit lines comprises a transistor, and the reference load comprises two current paths, each formed by one transistor. One of the two transistors is diode-connected, and the other is switchable by a switching network connected to the gate terminal of the respective transistor, for turning it off when only one reference current path is to be enabled, and for diode-connecting it when both the reference current paths are to be enabled.
摘要翻译： 一种包括通过选择电路连接到多个位线的负载的设备，以及连接到参考单元的负载，用于检测所选位线和参考单元中的电流。 连接到位线的负载包括晶体管，并且参考负载包括两个电流路径，每个由一个晶体管形成。 两个晶体管中的一个是二极管连接的，另一个晶体管可以由连接到相应晶体管的栅极端子的开关网络切换，以便在仅使能一个参考电流路径时将其关断，并且用于二极管连接 当两个参考电流路径都要使能时。
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公开(公告)号：US5546054A
公开(公告)日：1996-08-13
申请号：US377524
申请日：1995-01-20
申请人： Marco Maccarrone , Marco Olivo , Carla M. Golla
发明人： Marco Maccarrone , Marco Olivo , Carla M. Golla
CPC分类号： G05F3/262
摘要： A current source including a current mirror circuit and an active load circuit which form a reference branch, for setting a reference current value, and a mirroring branch, defining an output current value, connected between supply and ground. A voltage stabilizing transistor is interposed between the current mirror circuit and the load circuit in the reference branch only, and is so biased as to maintain its gate terminal at a predetermined voltage. As such, the potential with respect to ground of the drain terminal of the reference branch load transistor is fixed, so that its drain-source voltage drop (and the current through it) is substantially independent of supply voltage. The current source may be used to advantage in an oscillator for generating the: clock signal of a nonvolatile memory.
摘要翻译： 电流源包括形成用于设定参考电流值的参考支路的电流镜电路和有源负载电路以及连接在电源和地之间的限定输出电流值的镜像支路。 稳压晶体管仅插入在电流镜电路和参考支路中的负载电路之间，并被偏置以将其栅极端子保持在预定电压。 因此，参考分支负载晶体管的漏极端子的接地电位是固定的，使得其漏 - 源电压降（和通过它的电流）基本上不依赖于电源电压。 在振荡器中可以使用电流源来产生非易失性存储器的：时钟信号。
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公开(公告)号：US5532972A
公开(公告)日：1996-07-02
申请号：US391920
申请日：1995-02-21
申请人： Luigi Pascucci , Silvia Padoan , Carla M. Golla , Marco Maccarrone , Marco Olivo
发明人： Luigi Pascucci , Silvia Padoan , Carla M. Golla , Marco Maccarrone , Marco Olivo
CPC分类号： G11C7/02 , G11C16/32 , G11C7/1006 , G11C7/22
摘要： A circuit comprises a section generating a pulse signal for asynchronously enabling the read phases; a section generating precharge and detecting signals of adjustable duration, for controlling data reading from the memory and data supply to the output buffers; a section generating a noise suppressing signal for freezing the data in the output buffers during loading into the output circuits, and the duration of which is exactly equal to the propagation time of the data to the output circuits of the memory, as determined by propagating a data simulating signal in an output simulation circuit; a section generating a loading signal, the duration of which may be equal to that of the noise suppressing signal or extended by an extension circuit in the event the array presents slower elements which may thus be read; and a section generating a circuit reset signal.
摘要翻译： 电路包括产生用于异步地使读取相位的脉冲信号的部分; 产生预充电和检测可调节持续时间的信号的部分，用于控制从存储器读取数据并向输出缓冲器提供数据; 产生用于在加载到输出电路期间将输出缓冲器中的数据冻结的噪声抑制信号的部分，其持续时间恰好等于数据到存储器的输出电路的传播时间，如通过传播 输出仿真电路中的数据模拟信号; 产生负载信号的部分，其持续时间可以等于噪声抑制信号的延迟，或者在阵列呈现较慢的元素，由此可以被读取的情况下由扩展电路扩展; 以及产生电路复位信号的部分。
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公开(公告)号：US5563826A
公开(公告)日：1996-10-08
申请号：US422813
申请日：1995-04-17
申请人： Luigi Pascucci , Carla M. Golla , Marco Maccarrone
发明人： Luigi Pascucci , Carla M. Golla , Marco Maccarrone
摘要： A read circuit comprises at least one array branch connected to at least one bit line, and a reference branch connected to a reference line. The array and reference branches each comprise a precharge circuit and load interposed between the supply and the bit line and reference line respectively. The reference load is so formed as to generate a reference current which, during evaluation, is twice the current supplied to the bit line. The reference line is connected to an extra-current transistor which is only turned on during equalization so that, during equalization, the selected bit line is supplied with a high current approximating that supplied to the reference line. As such, if the cell to be read is written, the output voltage of the array branch is brought rapidly to its natural high value; whereas, if the cell to be read is erased, the output voltage may return to its low value when the extra-current transistor is turned off, thus permitting reading in advance.
摘要翻译： 读取电路包括连接到至少一个位线的至少一个阵列分支和连接到参考线的参考分支。 阵列和参考支路各自包括预充电电路和插入在电源和位线和参考线之间的负载。 参考负载被形成为产生参考电流，其在评估期间是提供给位线的电流的两倍。 参考线连接到在均衡期间仅导通的过电流晶体管，使得在均衡期间，所选择的位线被提供近似于提供给参考线的高电流。 因此，如果要读取的单元被写入，则阵列分支的输出电压迅速地达到其自然的高值; 而如果要读取的单元被擦除，则当超级晶体管截止时，输出电压可能返回到其低电平值，因此可以预先读取。
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7.发明授权
公开(公告)号：US5499217A
公开(公告)日：1996-03-12
申请号：US348461
申请日：1994-12-02
申请人： Luigi Pascucci , Carla M. Golla , Marco Maccarrone
发明人： Luigi Pascucci , Carla M. Golla , Marco Maccarrone
CPC分类号： G11C8/10
摘要： A memory line decoding driver is so biased that the P channel pull-up transistor biasing the final inverter conducts a high current during the line address transient phase, for rapidly charging the input of the final inverter, and is turned on weakly during the static phase between one address phase and another, for reducing current consumption. For which purpose, a voltage modulating stage alternatively connects the gate terminal of the pull-up transistor to a capacitor, with which the charge is distributed, and to the supply.
摘要翻译： 存储器线路解码驱动器被偏置，使得偏置最终的反相器的P沟道上拉晶体管在线路地址瞬态阶段期间导通高电流，以便对最终的反相器的输入进行快速充电，并且在静态期间弱 在一个地址阶段和另一个之间，以减少电流消耗。 为此，电压调制级将上拉晶体管的栅极端子交替地连接到电荷分配的电容器和电源。
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公开(公告)号：US5566114A
公开(公告)日：1996-10-15
申请号：US349783
申请日：1994-12-06
申请人： Luigi Pascucci , Carla M. Golla
发明人： Luigi Pascucci , Carla M. Golla
CPC分类号： G11C29/70
摘要： A redundancy circuitry for a semiconductor memory device comprising a matrix of memory elements and a plurality of programmable non-volatile memory registers. The non-volatile memory registers being programmable to store addresses of defective memory elements that must be replaced by redundancy memory elements. The redundancy circuitry comprises a combinatorial circuit supplied by address signals and supplying the non-volatile registers with an inhibition signal for inhibiting the selection of redundancy memory elements when a memory element of the matrix is addressed whose address coincides with the address stored in a non-programmed memory register.
摘要翻译： 一种用于半导体存储器件的冗余电路，包括存储元件矩阵和多个可编程非易失性存储寄存器。 非易失性存储器寄存器是可编程的，以存储必须由冗余存储器元件替代的缺陷存储器元件的地址。 冗余电路包括由地址信号提供的组合电路，并且当矩阵的存储元件被寻址时，向非易失性寄存器提供用于禁止冗余存储器元件的选择的禁止信号，其地址与存储在非易失性寄存器中的地址一致， 程序存储器寄存器。
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