公开(公告)号：US5801457A

公开(公告)日：1998-09-01

申请号：US749615

申请日：1996-11-18

申请人： Chang Hee Hong ,  John H. Pasternak

发明人： Chang Hee Hong ,  John H. Pasternak

IPC分类号： G11C5/00 ,  G11C5/14 ,  G11C7/10 ,  H02J9/06 ,  H02J1/00

CPC分类号： G11C7/1045 ,  G11C5/005 ,  G11C5/143 ,  H02J9/06 ,  Y10T307/696

摘要： A unit for maintaining the value of information regarding the state of a device during battery power includes one local latch per bit of state to be maintained. The latch is powered by a switched power supply which switches between main and battery power supplies. The latch latches the value of the bit of state when the value of the bit of state is valid and the power of the device is significant and maintains the value otherwise, typically during battery operation.

摘要翻译： 在电池供电期间用于维持关于装置的状态的信息的值的单元包括要维持的每位状态的一个本地锁存器。 闩锁由在主电源和电池电源之间切换的开关电源供电。 当状态位的值有效并且器件的电源有效并且通常在电池操作期间保持其它值时，锁存器锁存状态位的值。

公开(公告)号：US5912560A

公开(公告)日：1999-06-15

申请号：US806560

申请日：1997-02-25

申请人： John H. Pasternak

发明人： John H. Pasternak

IPC分类号： H02M3/07 ,  H03K17/06 ,  H03K3/01

CPC分类号： H03K17/063 ,  H02M3/073

摘要： A charge pump whose charge transfer switches are formed of charge transfer transistors and single pole, double throw (SPDT) switches each of which controls the gate of its corresponding transistor. Each SPDT switch has two throw contacts, one which is connected to the left diffusion of its corresponding charge transfer transistor and the other of which is connected to ground. Thus, the SPDT switch selectively connects the gate of the charge transfer transistor it controls between a diode connection (the first contact) and ground (the second contact). As a result, the charge transfer switches of the present invention are both fully on (when diode-connected) or fully off (when connected to ground).

摘要翻译： 一种电荷泵，其电荷转移开关由电荷转移晶体管和单极双掷（SPDT）开关形成，每个开关控制其相应晶体管的栅极。 每个SPDT开关具有两个触点，一个连接到其相应的电荷转移晶体管的左扩散，另一个连接到地。 因此，SPDT开关选择性地将其控制的电荷转移晶体管的栅极连接在二极管连接（第一触点）和地（第二触点）之间。 结果，本发明的电荷转移开关全部接通（二极管连接时）或完全断开（当接地时）。

公开(公告)号：US5568085A

公开(公告)日：1996-10-22

申请号：US242947

申请日：1994-05-16

申请人： Boaz Eitan ,  Reza Kazerounian ,  Alex Shubat ,  John H. Pasternak

发明人： Boaz Eitan ,  Reza Kazerounian ,  Alex Shubat ,  John H. Pasternak

IPC分类号： G05F3/24 ,  G05F1/10

CPC分类号： G05F3/242

摘要： A unit for stabilizing the voltage on a capacitive node of a memory array, such as a common node bit line (CNBL), is disclosed. The unit includes an amplifier connected to the CNBL line and to one voltage source and a leaker connected to the CNBL line and to the other voltage supply, where the two voltage supplies can be the positive and ground supplies. The leaker is much smaller then the amplifier thereby to remove current from the CNBL line when there is little or no activity in The memory array. An alternative version of the unit which is also operative for standby operation is disclosed. In this embodiment, there is a switchable high power unit activatable during an active mode and a low power unit. Both units include an amplifier and a leaker connected as in the previous embodiment. The leakers are much smaller then the amplifiers and the amplifier of the high power unit is much larger than the amplifier of the low power unit. The high power unit also includes control transistors for disabling its amplifier and leaker during the standby mode.

摘要翻译： 公开了一种用于稳定诸如公共节点位线（CNBL）的存储器阵列的电容性节点上的电压的单元。 该单元包括连接到CNBL线的放大器和连接到CNBL线和另一个电压源的一个电压源和漏斗，其中两个电压源可以是正和地电源。 漏电器比放大器小得多，从而当存储器阵列中存在很少或没有活动时，从CNBL线路中去除电流。 公开了一种也可用于备用操作的单元的替代版本。 在该实施例中，存在可激活的高功率单元，其可在活动模式和低功率单元期间激活。 两个单元包括如前述实施例中那样连接的放大器和漏斗。 泄漏器比放大器小得多，大功率单元的放大器比低功率单元的放大器大得多。 高功率单元还包括用于在待机模式期间禁用其放大器和漏斗的控制晶体管。

公开(公告)号：US06856551B2

公开(公告)日：2005-02-15

申请号：US10359993

申请日：2003-02-06

申请人： Nima Mokhlesi ,  John H. Pasternak

发明人： Nima Mokhlesi ,  John H. Pasternak

IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C11/34

CPC分类号： G11C16/0458 ,  G11C16/10 ,  G11C16/3454

摘要： A system and method for quickly and efficiently programming hard-to-program storage elements in non-volatile integrated memory devices is presented. A number of storage elements are simultaneously subjected to a programming process with the current flowing through the storage elements limited to a first level. As a portion of these storage elements reach a prescribed state, they are removed from the set of cells being programmed and the current limit on the elements that continue to be programmed is raised. The current level in these hard-to-program cells can be raised to a second, higher limit or unregulated.

公开(公告)号：US06577535B2

公开(公告)日：2003-06-10

申请号：US09785915

申请日：2001-02-16

申请人： John H. Pasternak

发明人： John H. Pasternak

IPC分类号： G11C1604

CPC分类号： G11C5/145 ,  G11C5/14 ,  G11C5/147 ,  G11C16/30

摘要： Techniques for producing and supplying various voltage levels within a memory system having multiple memory blocks (e.g., memory chips) are disclosed. The various voltage levels can be produced by charge pump and regulator circuitry within the memory system. The various voltage levels can be supplied to the multiple memory blocks through a power bus. According to one aspect of the invention, charge pump and regulator circuitry is not only provided within each of the memory blocks of a memory system, but also the charge pump and regulator circuits are not used to supply voltage signals to their own memory blocks. Instead, the charge pump and regulator circuits are used to supply voltage signals to other memory blocks.

公开(公告)号：US06522585B2

公开(公告)日：2003-02-18

申请号：US09865320

申请日：2001-05-25

申请人： John H. Pasternak

发明人： John H. Pasternak

IPC分类号： G11C1606

CPC分类号： G11C16/3404 ,  G11C16/0491 ,  G11C16/12 ,  G11C16/24

摘要： A technique for controlling the soft-program current in virtual-ground FLASH memory arrays is described. It is based on biasing the array bit-lines such that all current supplied to the array is used entirely towards the soft-programming of selected cells. The result is control of the soft-programming current and the programming rate of individual cell pairs. The benefit of soft-programming is then realized during the actual cell programming with the improved control of current and program rate. This is described with respect to an embodiment that uses source-side injection as the means for programming memory cells and with respect to a second embodiment based on a cell with dual floating gates.

摘要翻译： 描述了一种用于控制虚拟地FLASH存储器阵列中的软程序电流的技术。 它基于偏置阵列位线，使得提供给阵列的所有电流完全用于所选单元的软编程。 结果是控制软编程电流和单个单元对的编程速率。 然后在实际的单元编程中实现软编程的优点，改进了当前和程序速率的控制。 这相对于使用源侧注入作为用于编程存储器单元的装置并且关于基于具有双浮动栅极的单元的第二实施例的实施例进行了描述。

公开(公告)号：US6115272A

公开(公告)日：2000-09-05

申请号：US178050

申请日：1998-10-26

申请人： John H. Pasternak

发明人： John H. Pasternak

IPC分类号： H02M3/07 ,  H02M3/18

CPC分类号： H02M3/07

摘要： An internal supply generator includes a charge pump, at least one regulator and a pump controller. The charge pump generates a charge pump signal whose voltage is higher than an input supply voltage. Each regulator produces a generally stable internal supply from the charge pump signal. The pump controller activates the charge pump whenever the charge pump signal falls to within a predetermined voltage of the voltage level of one of the internal supplies.

摘要翻译： 内部电源发生器包括电荷泵，至少一个调节器和泵控制器。 电荷泵产生电压高于输入电源电压的电荷泵信号。 每个调节器从电荷泵信号产生一般稳定的内部电源。 每当电荷泵信号下降到其中一个内部电源的电压电平的预定电压内时，泵控制器激活电荷泵。

公开(公告)号：US5402014A

公开(公告)日：1995-03-28

申请号：US91795

申请日：1993-07-14

申请人： Arye Ziklik ,  Alexander Shubat ,  Yoram Cedar ,  John H. Pasternak

发明人： Arye Ziklik ,  Alexander Shubat ,  Yoram Cedar ,  John H. Pasternak

IPC分类号： H03K19/177 ,  H03K19/173

CPC分类号： H03K19/17708

摘要： An embodiment of this invention provides an integrated circuit (IC) having a configurable peripheral port which includes an input/output pin, a multiplexer coupled to the input/output pin, volatile configuration bits to control the multiplexer, and non-volatile configuration bits to control the multiplexer and override the volatile configuration bits. One embodiment of an IC also includes a peripheral port as above and functional units, such as programmable array logic (PAL) and erasable programmable read only memory (EPROM), coupled to the multiplexer. In another embodiment, a non-volatile configuration bit from a functional unit configures an input/output pin when the configuration bit is not needed by the functional unit.

摘要翻译： 本发明的实施例提供了一种具有可配置外围端口的集成电路（IC），其包括输入/​​输出引脚，耦合到输入/输出引脚的多路复用器，用于控制多路复用器的易失性配置位，以及非易失性配置位 控制多路复用器并覆盖易失性配置位。 IC的一个实施例还包括如上的外围端口和耦合到多路复用器的功能单元，诸如可编程阵列逻辑（PAL）和可擦除可编程只读存储器（EPROM）。 在另一个实施例中，当功能单元不需要配置位时，来自功能单元的非易失性配置位配置输入/输出引脚。