公开(公告)号：US20110303971A1

公开(公告)日：2011-12-15

申请号：US13157659

申请日：2011-06-10

申请人： Changwon Lee ,  Kihyun Hwang ,  Hanmei Choi ,  Sun Woo Lee ,  Junkyu Yang ,  Sunggil Kim ,  Jeonggil Lee ,  Seon-Ho Jo

发明人： Changwon Lee ,  Kihyun Hwang ,  Hanmei Choi ,  Sun Woo Lee ,  Junkyu Yang ,  Sunggil Kim ,  Jeonggil Lee ,  Seon-Ho Jo

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

摘要： A method for manufacturing a three-dimensional semiconductor memory includes forming a plurality of stacked structures disposed on a substrate to be spaced apart from each other, each of the stacked structures including a plurality of dielectric patterns and a plurality of polysilicon patterns alternately stacked, forming a metal layer to cover sidewalls of the stacked structures and a top surface of the substrate exposed between the stacked structures, and forming stacked gate electrodes on the substrate and a conductive line in the substrate by performing a silicidation process between the metal layer and each of the polysilicon patterns and the substrate.

摘要翻译： 一种三维半导体存储器的制造方法，其特征在于，在基板上形成多个层叠结构，使其彼此间隔开，所述堆叠结构中的每一个包括多个电介质图案和多个多晶硅图案，交替层叠，形成 覆盖层叠结构的侧壁的金属层和露出在层叠结构之间的基板的顶面，通过在金属层与金属层之间进行硅化处理，在基板上形成层叠的栅电极和基板的导电线 多晶硅图案和衬底。

公开(公告)号：US20100207185A1

公开(公告)日：2010-08-19

申请号：US12704365

申请日：2010-02-11

申请人： Sunwoo Lee ,  Sangwoo Lee ,  Changwon Lee ,  Jeonggil Lee

发明人： Sunwoo Lee ,  Sangwoo Lee ,  Changwon Lee ,  Jeonggil Lee

IPC分类号： H01L29/792

CPC分类号： H01L27/11582 ,  H01L21/28282 ,  H01L23/535 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/1159 ,  H01L29/4958 ,  H01L29/4966

摘要： A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern.

摘要翻译： 非易失性存储器件包括三维地布置在半导体衬底上的栅电极，从半导体衬底延伸并与栅电极的侧壁交叉的半导体图案，形成在半导体图案之间并形成在顶表面和底表面上的金属衬垫图案 以及形成在半导体图案和金属衬垫图案之间的电荷存储层。

公开(公告)号：US20120094453A1

公开(公告)日：2012-04-19

申请号：US13273935

申请日：2011-10-14

申请人： Hauk Han ,  Byoung-Kyu Lee ,  Jingi Hong ,  Changwon Lee ,  Eungjoon Lee ,  Je-Hyeon Park ,  Jeonggil Lee

发明人： Hauk Han ,  Byoung-Kyu Lee ,  Jingi Hong ,  Changwon Lee ,  Eungjoon Lee ,  Je-Hyeon Park ,  Jeonggil Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/7827 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/7926

摘要： Semiconductor devices and methods of fabricating semiconductor devices that may include forming an insulation structure including insulation patterns that are sequentially stacked and vertically separated from each other to provide gap regions between the insulation patterns, forming a first conductive layer filling the gap regions and covering two opposite sidewalls of the insulation structure, and forming a second conductive layer covering the first conductive layer. A thickness of the second conductive layer covering an upper sidewall of the insulation structure is greater than a thickness of the second conductive layer covering a lower sidewall of the insulation structure.

摘要翻译： 制造半导体器件的半导体器件和方法，其可以包括形成绝缘结构，所述绝缘结构包括彼此依次层叠并垂直分离的绝缘图案，以在绝缘图案之间提供间隙区域，形成填充间隙区域并覆盖两个相对的间隔区域的第一导电层 并且形成覆盖第一导电层的第二导电层。 覆盖绝缘结构的上侧壁的第二导电层的厚度大于覆盖绝缘结构的下侧壁的第二导电层的厚度。

公开(公告)号：US08679920B2

公开(公告)日：2014-03-25

申请号：US13273935

申请日：2011-10-14

申请人： Hauk Han ,  Byoung-Kyu Lee ,  Jingi Hong ,  Changwon Lee ,  Eungjoon Lee ,  Je-Hyeon Park ,  Jeonggil Lee

发明人： Hauk Han ,  Byoung-Kyu Lee ,  Jingi Hong ,  Changwon Lee ,  Eungjoon Lee ,  Je-Hyeon Park ,  Jeonggil Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/7827 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/7926

摘要： Semiconductor devices and methods of fabricating semiconductor devices that may include forming an insulation structure including insulation patterns that are sequentially stacked and vertically separated from each other to provide gap regions between the insulation patterns, forming a first conductive layer filling the gap regions and covering two opposite sidewalls of the insulation structure, and forming a second conductive layer covering the first conductive layer. A thickness of the second conductive layer covering an upper sidewall of the insulation structure is greater than a thickness of the second conductive layer covering a lower sidewall of the insulation structure.

摘要翻译： 制造半导体器件的半导体器件和方法，其可以包括形成绝缘结构，所述绝缘结构包括彼此依次层叠并垂直分离的绝缘图案，以在绝缘图案之间提供间隙区域，形成填充间隙区域并覆盖两个相对的间隔区域的第一导电层 并且形成覆盖第一导电层的第二导电层。 覆盖绝缘结构的上侧壁的第二导电层的厚度大于覆盖绝缘结构的下侧壁的第二导电层的厚度。

公开(公告)号：US08324677B2

公开(公告)日：2012-12-04

申请号：US12704365

申请日：2010-02-11

申请人： Sunwoo Lee ,  Sangwoo Lee ,  Changwon Lee ,  Jeonggil Lee

发明人： Sunwoo Lee ,  Sangwoo Lee ,  Changwon Lee ,  Jeonggil Lee

IPC分类号： H01L29/72

CPC分类号： H01L27/11582 ,  H01L21/28282 ,  H01L23/535 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/1159 ,  H01L29/4958 ,  H01L29/4966

摘要： A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern.

摘要翻译： 非易失性存储器件包括三维地布置在半导体衬底上的栅电极，从半导体衬底延伸并与栅电极的侧壁交叉的半导体图案，形成在半导体图案之间并形成在顶表面和底表面上的金属衬垫图案 以及形成在半导体图案和金属衬垫图案之间的电荷存储层。

公开(公告)号：US20140220750A1

公开(公告)日：2014-08-07

申请号：US14171056

申请日：2014-02-03

申请人： Woonghee Sohn ,  Kihyun Yun ,  Myoungbum Lee ,  Jeonggil Lee ,  Tai-Soo Lim ,  Yong Chae Jung

发明人： Woonghee Sohn ,  Kihyun Yun ,  Myoungbum Lee ,  Jeonggil Lee ,  Tai-Soo Lim ,  Yong Chae Jung

IPC分类号： H01L27/115

CPC分类号： H01L27/11556 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

摘要： Provided are a semiconductor device and a method of fabricating the same. The method may include forming an electrode structure including insulating layers and electrode layers alternatingly stacked on a substrate, forming a channel hole to penetrate the electrode structure, forming a data storage layer on a sidewall of the channel hole, and forming a semiconductor pattern on a sidewall of the data storage layer to be electrically connected to the substrate. The electrode layers may be metal-silicide layers, and the insulating layers and the electrode layers may be formed in an in-situ manner using the same deposition system.

摘要翻译： 提供半导体器件及其制造方法。 该方法可以包括形成包括绝缘层和交替层叠在基板上的电极层的电极结构，形成穿透电极结构的通道孔，在通道孔的侧壁上形成数据存储层，以及在通孔上形成半导体图案 数据存储层的侧壁将被电连接到基板。 电极层可以是金属硅化物层，并且可以使用相同的沉积系统以原位方式形成绝缘层和电极层。

公开(公告)号：US09997462B2

公开(公告)日：2018-06-12

申请号：US15581782

申请日：2017-04-28

申请人： Jooyeon Ha ,  Jeonggil Lee ,  Dohyung Kim ,  Keun Lee ,  HyunSeok Lim ,  Hauk Han

发明人： Jooyeon Ha ,  Jeonggil Lee ,  Dohyung Kim ,  Keun Lee ,  HyunSeok Lim ,  Hauk Han

IPC分类号： H01L27/115 ,  H01L23/535 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/532 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/792 ,  H01L29/788 ,  H01L27/11578

CPC分类号： H01L23/535 ,  H01L23/53266 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： A memory device includes a vertical string of nonvolatile memory cells on a substrate, along with a ground selection transistor extending between the vertical string of nonvolatile memory cells and the substrate. The ground selection transistor can have a current carrying terminal electrically coupled to a channel region of a nonvolatile memory cell in the vertical string of nonvolatile memory cells. The ground selection transistor includes a gate electrode associated with a ground selection line of the memory device. This gate electrode includes: (i) a mask pattern, (ii) a barrier metal layer of a first material extending opposite a sidewall of the mask pattern and (iii) a metal pattern of a second material different from the first material extending between at least a portion of the barrier metal layer and the mask pattern.

公开(公告)号：US09953997B2

公开(公告)日：2018-04-24

申请号：US15249590

申请日：2016-08-29

申请人： Joyoung Park ,  Hauk Han ,  Seok-Won Lee ,  Jeonggil Lee ,  Jinwoo Park ,  Kihyun Yoon ,  Hyunseok Lim ,  Jooyeon Ha

发明人： Joyoung Park ,  Hauk Han ,  Seok-Won Lee ,  Jeonggil Lee ,  Jinwoo Park ,  Kihyun Yoon ,  Hyunseok Lim ,  Jooyeon Ha

IPC分类号： H01L23/52 ,  H01L27/11582 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC分类号： H01L27/11582 ,  H01L21/76816 ,  H01L21/76865 ,  H01L21/76876 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L27/1157

摘要： Disclosed is a semiconductor memory device including stacks on a substrate, a vertical channel portion connected to the substrate through each of the stacks, and a separation pattern disposed between the stacks. Each of the stacks may include a plurality of gate electrodes stacked on the substrate and insulating patterns interposed between the gate electrodes. Each of the gate electrodes may include a first metal pattern, which is disposed between the insulating patterns to define a recess region recessed toward the vertical channel portion, and a second metal pattern disposed in the recess region. The first and second metal patterns may contain the same metallic material and may have mean grain sizes different from each other.

公开(公告)号：US09373628B2

公开(公告)日：2016-06-21

申请号：US14171056

申请日：2014-02-03

申请人： Woonghee Sohn ,  Kihyun Yun ,  Myoungbum Lee ,  Jeonggil Lee ,  Tai-Soo Lim ,  Yong Chae Jung

发明人： Woonghee Sohn ,  Kihyun Yun ,  Myoungbum Lee ,  Jeonggil Lee ,  Tai-Soo Lim ,  Yong Chae Jung

IPC分类号： H01L21/336 ,  H01L27/115 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11556 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

摘要： Provided are a semiconductor device and a method of fabricating the same. The method may include forming an electrode structure including insulating layers and electrode layers alternatingly stacked on a substrate, forming a channel hole to penetrate the electrode structure, forming a data storage layer on a sidewall of the channel hole, and forming a semiconductor pattern on a sidewall of the data storage layer to be electrically connected to the substrate. The electrode layers may be metal-silicide layers, and the insulating layers and the electrode layers may be formed in an in-situ manner using the same deposition system.

摘要翻译： 提供半导体器件及其制造方法。 该方法可以包括形成包括绝缘层和交替层叠在基板上的电极层的电极结构，形成穿透电极结构的通道孔，在通道孔的侧壁上形成数据存储层，以及在通孔上形成半导体图案 数据存储层的侧壁将被电连接到基板。 电极层可以是金属硅化物层，并且可以使用相同的沉积系统以原位方式形成绝缘层和电极层。

公开(公告)号：US09224753B2

公开(公告)日：2015-12-29

申请号：US14599933

申请日：2015-01-19

申请人： Tai-Soo Lim ,  Jeonggil Lee ,  Yeon-Sil Sohn ,  Woonghee Sohn ,  Myoungbum Lee ,  Yong Chae Jung

发明人： Tai-Soo Lim ,  Jeonggil Lee ,  Yeon-Sil Sohn ,  Woonghee Sohn ,  Myoungbum Lee ,  Yong Chae Jung

IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L29/49

CPC分类号： H01L27/11582 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/4975 ,  H01L29/4991 ,  H01L29/66666 ,  H01L29/7827

摘要： Provided are a semiconductor memory device and a fabricating method thereof. The device includes a stack including vertical channel structures that penetrate insulating patterns and gate electrodes that are alternately and repeatedly stacked on each other. Each of the gate electrodes includes first and second gate conductive layers. In a first region between an outer side of the stack and the vertical channel structures, the first gate conductive layer is adjacent to the vertical channel structures and includes a truncated end portion, the second gate conductive layer has a portion adjacent to the vertical channel structures and covered by a corresponding one of the first gate conductive layer and an opposite portion that is not covered with the first gate conductive layer. In a second region between the vertical channel structures, the first gate conductive layer may be extended to continuously cover surfaces of the second gate conductive layer.

摘要翻译： 提供半导体存储器件及其制造方法。 该装置包括堆叠，其包括穿透绝缘图案的垂直沟道结构和彼此交替重复堆叠的栅电极。 每个栅极电极包括第一和第二栅极导电层。 在堆叠的外侧和垂直沟道结构之间的第一区域中，第一栅极导电层与垂直沟道结构相邻并且包括截头端部，第二栅极导电层具有与垂直沟道结构相邻的部分 并且被第一栅极导电层中的相应一个和未被第一栅极导电层覆盖的相对部分覆盖。 在垂直沟道结构之间的第二区域中，第一栅极导电层可以被延伸以连续地覆盖第二栅极导电层的表面。