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    Semiconductor memory device and method of fabricating the same
    1.
    发明授权
    Semiconductor memory device and method of fabricating the same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US09224753B2

    公开(公告)日：2015-12-29

    申请号：US14599933

    申请日：2015-01-19

    申请人： Tai-Soo Lim ,  Jeonggil Lee ,  Yeon-Sil Sohn ,  Woonghee Sohn ,  Myoungbum Lee ,  Yong Chae Jung

    发明人： Tai-Soo Lim ,  Jeonggil Lee ,  Yeon-Sil Sohn ,  Woonghee Sohn ,  Myoungbum Lee ,  Yong Chae Jung

    IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L29/49

    CPC分类号： H01L27/11582 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/4975 ,  H01L29/4991 ,  H01L29/66666 ,  H01L29/7827

    摘要： Provided are a semiconductor memory device and a fabricating method thereof. The device includes a stack including vertical channel structures that penetrate insulating patterns and gate electrodes that are alternately and repeatedly stacked on each other. Each of the gate electrodes includes first and second gate conductive layers. In a first region between an outer side of the stack and the vertical channel structures, the first gate conductive layer is adjacent to the vertical channel structures and includes a truncated end portion, the second gate conductive layer has a portion adjacent to the vertical channel structures and covered by a corresponding one of the first gate conductive layer and an opposite portion that is not covered with the first gate conductive layer. In a second region between the vertical channel structures, the first gate conductive layer may be extended to continuously cover surfaces of the second gate conductive layer.

    摘要翻译： 提供半导体存储器件及其制造方法。 该装置包括堆叠，其包括穿透绝缘图案的垂直沟道结构和彼此交替重复堆叠的栅电极。 每个栅极电极包括第一和第二栅极导电层。 在堆叠的外侧和垂直沟道结构之间的第一区域中，第一栅极导电层与垂直沟道结构相邻并且包括截头端部，第二栅极导电层具有与垂直沟道结构相邻的部分 并且被第一栅极导电层中的相应一个和未被第一栅极导电层覆盖的相对部分覆盖。 在垂直沟道结构之间的第二区域中，第一栅极导电层可以被延伸以连续地覆盖第二栅极导电层的表面。

    Semiconductor Memory Device and Method of Fabricating the Same
    2.
    发明申请
    Semiconductor Memory Device and Method of Fabricating the Same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US20140220750A1

    公开(公告)日：2014-08-07

    申请号：US14171056

    申请日：2014-02-03

    申请人： Woonghee Sohn ,  Kihyun Yun ,  Myoungbum Lee ,  Jeonggil Lee ,  Tai-Soo Lim ,  Yong Chae Jung

    发明人： Woonghee Sohn ,  Kihyun Yun ,  Myoungbum Lee ,  Jeonggil Lee ,  Tai-Soo Lim ,  Yong Chae Jung

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11556 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

    摘要： Provided are a semiconductor device and a method of fabricating the same. The method may include forming an electrode structure including insulating layers and electrode layers alternatingly stacked on a substrate, forming a channel hole to penetrate the electrode structure, forming a data storage layer on a sidewall of the channel hole, and forming a semiconductor pattern on a sidewall of the data storage layer to be electrically connected to the substrate. The electrode layers may be metal-silicide layers, and the insulating layers and the electrode layers may be formed in an in-situ manner using the same deposition system.

    摘要翻译： 提供半导体器件及其制造方法。 该方法可以包括形成包括绝缘层和交替层叠在基板上的电极层的电极结构，形成穿透电极结构的通道孔，在通道孔的侧壁上形成数据存储层，以及在通孔上形成半导体图案 数据存储层的侧壁将被电连接到基板。 电极层可以是金属硅化物层，并且可以使用相同的沉积系统以原位方式形成绝缘层和电极层。

    Semiconductor Devices And Methods Of Fabricating The Same
    6.
    发明申请
    Semiconductor Devices And Methods Of Fabricating The Same 有权
    半导体器件及其制造方法

    公开(公告)号：US20120094453A1

    公开(公告)日：2012-04-19

    申请号：US13273935

    申请日：2011-10-14

    申请人： Hauk Han ,  Byoung-Kyu Lee ,  Jingi Hong ,  Changwon Lee ,  Eungjoon Lee ,  Je-Hyeon Park ,  Jeonggil Lee

    发明人： Hauk Han ,  Byoung-Kyu Lee ,  Jingi Hong ,  Changwon Lee ,  Eungjoon Lee ,  Je-Hyeon Park ,  Jeonggil Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7827 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/7926

    摘要： Semiconductor devices and methods of fabricating semiconductor devices that may include forming an insulation structure including insulation patterns that are sequentially stacked and vertically separated from each other to provide gap regions between the insulation patterns, forming a first conductive layer filling the gap regions and covering two opposite sidewalls of the insulation structure, and forming a second conductive layer covering the first conductive layer. A thickness of the second conductive layer covering an upper sidewall of the insulation structure is greater than a thickness of the second conductive layer covering a lower sidewall of the insulation structure.

    摘要翻译： 制造半导体器件的半导体器件和方法，其可以包括形成绝缘结构，所述绝缘结构包括彼此依次层叠并垂直分离的绝缘图案，以在绝缘图案之间提供间隙区域，形成填充间隙区域并覆盖两个相对的间隔区域的第一导电层 并且形成覆盖第一导电层的第二导电层。 覆盖绝缘结构的上侧壁的第二导电层的厚度大于覆盖绝缘结构的下侧壁的第二导电层的厚度。