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1.发明授权Integrated circuit test coverage evaluation and adjustment mechanism and method 失效集成电路测试覆盖评估与调整机制与方法公开(公告)号：US06212667B1
公开(公告)日：2001-04-03
申请号：US09126142
申请日：1998-07-30
IPC分类号： G06F1750
CPC分类号： G01R31/31835
摘要： Testcases are run to test the design of an integrated circuit. The coverage of the testcases is evaluated and compared against one or more microarchitecture models that define the behavior of a portion of the integrated circuit. If the coverage of the testcases is not adequate, new testcases are generated to test the previously untested behavior specified in the microarchitecture models.
摘要翻译： 测试仪用于测试集成电路的设计。 对测试用例的覆盖率进行评估，并与一个或多个定义集成电路的一部分行为的微架构模型进行比较。 如果测试用例的覆盖范围不够，则会生成新的测试用例，以测试微体系结构模型中指定的以前未测试的行为。
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2.发明授权Apparatus for randomizing instruction thread interleaving in a multi-thread processor 有权用于在多线程处理器中随机化指令线程交错的装置公开(公告)号：US08145885B2
公开(公告)日：2012-03-27
申请号：US12112859
申请日：2008-04-30
CPC分类号： G06F9/3851
摘要： A processor interleaves instructions according to a priority rule which determines the frequency with which instructions from each respective thread are selected and added to an interleaved stream of instructions to be processed in the data processor. The frequency with which each thread is selected according to the rule may be based on the priorities assigned to the instruction threads. A randomization is inserted into the interleaving process so that the selection of an instruction thread during any particular clock cycle is not based solely by the priority rule, but is also based in part on a random or pseudo random element. This randomization is inserted into the instruction thread selection process so as to vary the order in which instructions are selected from the various instruction threads while preserving the overall frequency of thread selection (i.e. how often threads are selected) set by the priority rule.
摘要翻译： A处理器根据优先级规则对指令进行交织，该优先级规则确定选择来自每个相应线程的指令的频率，并将其附加到要在数据处理器中处理的交错指令流。 根据规则选择每个线程的频率可以基于分配给指令线程的优先级。 随机化被插入到交织处理中，使得在任何特定时钟周期期间指令线程的选择不仅仅基于优先级规则，而且还部分地基于随机或伪随机元素。 该随机化被插入到指令线程选择处理中，以便改变从各种指令线程中选择指令的顺序，同时保持由优先级规则设置的线程选择的总体频率（即选择多少线程）。
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3.发明授权Apparatus for adjusting instruction thread priority in a multi-thread processor 有权用于在多线程处理器中调整指令线程优先级的装置公开(公告)号：US07827388B2
公开(公告)日：2010-11-02
申请号：US12044846
申请日：2008-03-07
CPC分类号： G06F9/4818 , G06F9/3851
摘要： Each instruction thread in a SMT processor is associated with a software assigned base input processing priority. Unless some predefined event or circumstance occurs with an instruction being processed or to be processed, the base input processing priorities of the respective threads are used to determine the interleave frequency between the threads according to some instruction interleave rule. However, upon the occurrence of some predefined event or circumstance in the processor related to a particular instruction thread, the base input processing priority of one or more instruction threads is adjusted to produce one more adjusted priority values. The instruction interleave rule is then enforced according to the adjusted priority value or values together with any base input processing priority values that have not been subject to adjustment.
摘要翻译： SMT处理器中的每个指令线程与软件分配的基本输入处理优先级相关联。 除非正在处理或要处理的指令发生一些预定义的事件或情况，否则各个线程的基本输入处理优先级用于根据某种指令交错规则来确定线程之间的交织频率。 然而，在与特定指令线程相关的处理器中发生某些预定义的事件或环境时，调整一个或多个指令线程的基本输入处理优先级以产生一个更多调整的优先级值。 然后根据调整后的优先级值或与未经调整的任何基本输入处理优先级值一起实施指令交错规则。
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4.发明授权Apparatus and method for adjusting instruction thread priority in a multi-thread processor 有权用于调整多线程处理器中指令线程优先级的装置和方法公开(公告)号：US07401207B2
公开(公告)日：2008-07-15
申请号：US10424529
申请日：2003-04-25
CPC分类号： G06F9/4818 , G06F9/3851
摘要： Each instruction thread in a SMT processor is associated with a software assigned base input processing priority. Unless some predefined event or circumstance occurs with an instruction being processed or to be processed, the base input processing priorities of the respective threads are used to determine the interleave frequency between the threads according to some instruction interleave rule. However, upon the occurrence of some predefined event or circumstance in the processor related to a particular instruction thread, the base input processing priority of one or more instruction threads is adjusted to produce one more adjusted priority values. The instruction interleave rule is then enforced according to the adjusted priority value or values together with any base input processing priority values that have not been subject to adjustment.
摘要翻译： SMT处理器中的每个指令线程与软件分配的基本输入处理优先级相关联。 除非正在处理或要处理的指令发生一些预定义的事件或情况，否则各个线程的基本输入处理优先级用于根据某种指令交错规则来确定线程之间的交织频率。 然而，在与特定指令线程相关的处理器中发生某些预定义的事件或环境时，调整一个或多个指令线程的基本输入处理优先级以产生一个更多调整的优先级值。 然后根据调整后的优先级值或与未经调整的任何基本输入处理优先级值一起实施指令交错规则。
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5.发明申请APPARATUS FOR SELECTING AN INSTRUCTION THREAD FOR PROCESSING IN A MULTI-THREAD PROCESSOR 审中-公开选择用于多线程处理器处理的指令螺纹的装置公开(公告)号：US20080162904A1
公开(公告)日：2008-07-03
申请号：US12048171
申请日：2008-03-13
IPC分类号： G06F9/38
CPC分类号： G06F9/3851
摘要： The selection between instruction threads in a SMT processor for the purpose of interleaving instructions from the different instruction threads may be modified to accommodate certain processor events or conditions. During each processor clock cycle, an interleave rule enforcement component produces at least one base instruction thread selection signal that indicates a particular one of the instruction threads for passing an instruction from that particular thread into a stream of interleaved instructions. Thread selection modification is provided by an interleave modification component that generates a final thread selection signal based upon the base thread selection signal and a feedback signal derived from one or more conditions or events in the various processor elements. This final thread selection signal may indicate the same instruction thread indicated by the base thread selection signal or a different one of the instruction threads for passing an instruction into the interleaved stream of instructions.
摘要翻译： 可以修改SMT处理器中用于交织来自不同指令线程的指令的指令线程之间的选择以适应某些处理器事件或条件。 在每个处理器时钟周期期间，交错规则实施部件产生至少一个基本指令线程选择信号，其指示用于将指令从该特定线程传递到交错指令流中的特定指令线程。 线程选择修改由交织修改组件提供，交织修改组件基于基本线程选择信号和从各种处理器元件中的一个或多个条件或事件导出的反馈信号生成最后的线程选择信号。 该最终线程选择信号可以指示由基线程选择信号指示的相同指令线程或用于将指令传递到交错指令流的指令线程中的不同指令线程。
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6.发明授权Generating partition corresponding real address in partitioned mode supporting system 有权在分区模式支持系统中生成分区对应的实际地址公开(公告)号：US06438671B1
公开(公告)日：2002-08-20
申请号：US09346206
申请日：1999-07-01
申请人： Richard William Doing , Ronald Nick Kalla , Stephen Joseph Schwinn , Edward John Silha , Kenichi Tsuchiya
发明人： Richard William Doing , Ronald Nick Kalla , Stephen Joseph Schwinn , Edward John Silha , Kenichi Tsuchiya
IPC分类号： G06F1206
CPC分类号： G06F9/3804 , G06F9/3842 , G06F9/3851 , G06F9/5077 , G06F12/0284 , G06F12/1036 , G06F12/109 , G06F12/1491
摘要： A processor supports logical partitioning of a computer system. Logical partitions isolate the real address spaces of processes executing on different processors and the hardware resources that include processors. However, this multithreaded processor system can dynamically reallocate hardware resources including the processors among logical partitions. An ultra-privileged supervisor process, called a hypervisor, regulates the logical partitions. Preferably, the processor supports hardware multithreading, each thread independently capable of being in either hypervisor, supervisor, or problem state. The processor assigns certain generated addresses to its logical partition, preferably by concatenating certain high order bits from a special register with lower order bits of the generated address. A separate range check mechanism concurrently verifies that these high order effective address bits are in fact 0, and generates an error signal if they are not. In the preferred embodiment, instruction addresses from either active or dormant threads can be pre-fetched in anticipation of execution. In the preferred embodiment, the processor supports different environments which use the hypervisor, supervisor and problem states differently.
摘要翻译： 处理器支持计算机系统的逻辑分区。 逻辑分区隔离在不同处理器上执行的进程的真实地址空间以及包含处理器的硬件资源。 然而，该多线程处理器系统可以在逻辑分区中动态地重新分配包括处理器在内的硬件资源。 一个超级特权的管理程序，称为管理程序，它调节逻辑分区。 优选地，处理器支持硬件多线程，每个线程独立地能够处于管理程序，管理程序或问题状态中。 处理器将某些生成的地址分配给其逻辑分区，优选地通过将特定寄存器中的某些高阶位与所生成的地址的较低位相连。 单独的范围检查机制同时验证这些高阶有效地址位实际上为0，并且如果它们不是，则产生错误信号。 在优选实施例中，来自主动或休眠线程的指令地址可以预期执行。 在优选实施例中，处理器支持使用管理程序，主管和问题状态不同的不同环境。
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7.发明授权Processor system and methods of triggering a block move using a system bus write command initiated by user code 失效使用由用户代码启动的系统总线写入命令来触发块移动的处理器系统和方法公开(公告)号：US08281075B2
公开(公告)日：2012-10-02
申请号：US12423355
申请日：2009-04-14
申请人： Lakshminarayana Baba Arimilli , Brian Mitchell Bass , David Wayne Cummings , Bernard Charles Drerup , Guy Lynn Guthrie , Ronald Nick Kalla , Hugh Shen , Michael Steven Siegel , William John Starke , Derek Edward Williams
发明人： Lakshminarayana Baba Arimilli , Brian Mitchell Bass , David Wayne Cummings , Bernard Charles Drerup , Guy Lynn Guthrie , Ronald Nick Kalla , Hugh Shen , Michael Steven Siegel , William John Starke , Derek Edward Williams
CPC分类号： G06F12/1458 , G06F9/30047 , G06F9/30087 , G06F12/0893
摘要： A technique for triggering a system bus write command with user code includes identifying a specific store-type instruction in a user instruction sequence. The specific store-type instruction is converted into a specific request-type command, which is configured to include core permission controls (that are stored in core configuration registers of a processor core by a trusted kernel) and user created data (stored in a cache memory). Slave devices are configured through register space (that is only accessible by the trusted kernel) with respective slave permission controls. The specific request-type command is then transmitted from the cache memory, via a system bus. In this case, the slave devices that receive the specific request-type command process the specific request-type command when the core permission controls are the same as the respective slave permission controls. The trusted kernel may be included in a hypervisor or an operating system.
摘要翻译： 用户代码触发系统总线写命令的技术包括识别用户指令序列中的特定存储型指令。 特定存储型指令被转换成特定的请求类型命令，其被配置为包括核心权限控制（存储在可信内核中的处理器核心的核心配置寄存器中）和用户创建的数据（存储在高速缓存中） 记忆）。 从设备通过具有相应从属权限控制的寄存器空间（可由可信内核访问）进行配置。 然后，经由系统总线从高速缓冲存储器发送特定的请求类型命令。 在这种情况下，当核心权限控制与相应从属许可控制相同时，接收特定请求类型命令的从设备处理特定请求类型命令。 可信内核可能包含在管理程序或操作系统中。
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8.发明申请APPARATUS FOR RANDOMIZING INSTRUCTION THREAD INTERLEAVING IN A MULTI-THREAD PROCESSOR 有权用于在多线程处理器中指示线程交叉的随机设备公开(公告)号：US20080209426A1
公开(公告)日：2008-08-28
申请号：US12112859
申请日：2008-04-30
IPC分类号： G06F9/30
CPC分类号： G06F9/3851
摘要： A processor interleaves instructions according to a priority rule which determines the frequency with which instructions from each respective thread are selected and added to an interleaved stream of instructions to be processed in the data processor. The frequency with which each thread is selected according to the rule may be based on the priorities assigned to the instruction threads. A randomization is inserted into the interleaving process so that the selection of an instruction thread during any particular clock cycle is not based solely by the priority rule, but is also based in part on a random or pseudo random element. This randomization is inserted into the instruction thread selection process so as to vary the order in which instructions are selected from the various instruction threads while preserving the overall frequency of thread selection (i.e. how often threads are selected) set by the priority rule.
摘要翻译： A处理器根据优先级规则对指令进行交织，该优先级规则确定选择来自每个相应线程的指令的频率，并将其附加到要在数据处理器中处理的交错指令流。 根据规则选择每个线程的频率可以基于分配给指令线程的优先级。 随机化被插入到交织处理中，使得在任何特定时钟周期期间指令线程的选择不仅仅基于优先级规则，而且还部分地基于随机或伪随机元素。 该随机化被插入到指令线程选择处理中，以便改变从各种指令线程中选择指令的顺序，同时保持由优先级规则设置的线程选择的总体频率（即选择多少线程）。
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9.发明授权Method and logical apparatus for switching between single-threaded and multi-threaded execution states in a simultaneous multi-threaded (SMT) processor 失效用于在同时多线程（SMT）处理器中在单线程和多线程执行状态之间切换的方法和逻辑设备公开(公告)号：US07155600B2
公开(公告)日：2006-12-26
申请号：US10422648
申请日：2003-04-24
CPC分类号： G06F9/485
摘要： A method and logical apparatus for switching between single-threaded and multi-threaded execution states within a simultaneous multi-threaded (SMT) processor provides a mechanism for switching between single-threaded and multi-threaded execution. The processor receives an instruction specifying a transition from a single-threaded to a multi-threaded mode or vice-versa and halts execution of all threads executing on the processor. Internal control logic controls a sequence of events that ends instruction prefetching, dispatch of new instructions, interrupt processing and maintenance operations and waits for operation of the processor to complete for instructions that are in process. Then, the logic determines one or more threads to start in conformity with a thread enable state specifying the enable state of multiple threads and reallocates various resources, dividing them between threads if multiple threads are specified for further execution (multi-threaded mode) or allocating substantially all of the resources to a single thread if further execution is specified as single-threaded mode. The processor then starts execution of the remaining enabled threads.
摘要翻译： 用于在同时多线程（SMT）处理器中的单线程和多线程执行状态之间切换的方法和逻辑设备提供了在单线程和多线程执行之间进行切换的机制。 处理器接收指定从单线程转换到多线程模式或反之亦然的指令，并停止在处理器上执行的所有线程的执行。 内部控制逻辑控制结束指令预取，调度新指令，中断处理和维护操作的事件序列，并等待处理器的操作完成以处理正在进行的指令。 然后，逻辑根据指定多个线程的使能状态的线程使能状态确定一个或多个线程，以重新分配各种资源，如果多个线程被指定用于进一步执行（多线程模式）或分配 如果进一步执行被指定为单线程模式，则基本上所有的资源到单个线程。 然后，处理器开始执行剩余的已启用线程。
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公开(公告)号：US07051221B2
公开(公告)日：2006-05-23
申请号：US10425399
申请日：2003-04-28
IPC分类号： G06F1/32
CPC分类号： G06F9/3017 , G06F1/206 , G06F1/3203 , G06F1/324 , G06F1/3287 , G06F9/30149 , G06F9/3802 , G06F9/3851 , G06F9/3853 , G06F9/3867 , G06F9/3885 , Y02D10/126 , Y02D10/16 , Y02D10/171 , Y02D50/20
摘要： A microprocessor includes a functional block having dynamic power savings circuitry, a functional block control circuit, and a thermal control unit. The functional block control circuits are capable of altering performance characteristics of their associated functional blocks automatically upon detecting an over temperature condition. The thermal control unit receives an over-temperature signal indicating a processor temperature exceeding a threshold and invokes the one or more of the functional block control units in response to the signal. The functional block control units respond to signals from the thermal control unit by reducing processor activity, slowing processor performance, or both. The reduced activity that results causes the dynamic power saving circuitry to engage. The functional block control units can throttle performance by numerous means including reducing the exploitable parallelism within the processor, suspending out-of-order execution, reducing effective resource size, and the like.
摘要翻译： 微处理器包括具有动态功率节省电路的功能块，功能块控制电路和热控制单元。 功能块控制电路能够在检测到过温度条件时自动改变其相关功能块的性能特性。 热控制单元接收指示处理器温度超过阈值的过温度信号，并响应于该信号调用一个或多个功能块控制单元。 功能块控制单元通过减少处理器活动，降低处理器性能或两者来响应来自热控制单元的信号。 导致动态省电电路参与的活动减少。 功能块控制单元可以通过多种方式来抑制性能，包括减少处理器内可利用的并行性，暂停无序执行，减少有效的资源大小等。
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