公开(公告)号：US07662665B2

公开(公告)日：2010-02-16

申请号：US11655844

申请日：2007-01-22

申请人： Chen-Shien Chen ,  Kuo-Chin Chang ,  Szu-Wei Lu ,  Pei-Haw Tsao ,  Chung-Yu Wang ,  Han-Liang Tseng ,  Mirng-Ji Lii

发明人： Chen-Shien Chen ,  Kuo-Chin Chang ,  Szu-Wei Lu ,  Pei-Haw Tsao ,  Chung-Yu Wang ,  Han-Liang Tseng ,  Mirng-Ji Lii

IPC分类号： H01L21/00

CPC分类号： H01L23/49816 ,  H01L21/4853 ,  H01L23/49827 ,  H01L24/02 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/02319 ,  H01L2224/02321 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00

摘要： A method for fabricating a semiconductor package is provided. In one embodiment, a semiconductor chip having a plurality of exposed conductive layers thereon is provided. A first substrate having a first surface and a second surface is provided, the first surface having a plurality of exposed via plugs thereunder. The semiconductor chip is bonded to the first substrate, wherein the plurality of exposed conductor layers are aligned and in contact with the surfaces of the exposed via plugs. A portion of the second surface of the first substrate is then removed to expose the opposite ends of the plurality of via plugs. A plurality of UBM layers is formed on the surfaces of the opposite ends of the plurality of via plugs. A plurality of solder bumps is formed and mounted on the UBM layers. A second substrate having a first surface and a second surface is provided, the solder bumps being mounted to the first surface of the second substrate. A plurality of solder balls is formed and mounted to the second surface of the second substrate. A third substrate is mounted to the solder balls.

摘要翻译： 提供一种制造半导体封装的方法。 在一个实施例中，提供其上具有多个暴露的导电层的半导体芯片。 提供具有第一表面和第二表面的第一基底，所述第一表面在其下具有多个暴露的通孔塞。 半导体芯片被接合到第一基板，其中多个暴露的导体层被对准并且与暴露的通孔塞的表面接触。 然后去除第一基板的第二表面的一部分以暴露多个通孔塞的相对端。 在多个通孔塞的相对端的表面上形成多个UBM层。 多个焊料凸起形成并安装在UBM层上。 提供具有第一表面和第二表面的第二基底，焊料凸块安装到第二基底的第一表面。 多个焊球形成并安装在第二基板的第二表面上。 第三衬底安装到焊球。

公开(公告)号：US20080174002A1

公开(公告)日：2008-07-24

申请号：US11655844

申请日：2007-01-22

申请人： Chen-Shien Chen ,  Kuo-Chin Chang ,  Szu-Wei Lu ,  Pei-Haw Tsao ,  Chung-Yu Wang ,  Han-Liang Tseng ,  Mirng-Ji Lii

发明人： Chen-Shien Chen ,  Kuo-Chin Chang ,  Szu-Wei Lu ,  Pei-Haw Tsao ,  Chung-Yu Wang ,  Han-Liang Tseng ,  Mirng-Ji Lii

IPC分类号： H01L23/488 ,  H01L21/00

CPC分类号： H01L23/49816 ,  H01L21/4853 ,  H01L23/49827 ,  H01L24/02 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/02319 ,  H01L2224/02321 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00

摘要： A method for fabricating a semiconductor package is provided. In one embodiment, a semiconductor chip having a plurality of exposed conductive layers thereon is provided. A first substrate having a first surface and a second surface is provided, the first surface having a plurality of exposed via plugs thereunder. The semiconductor chip is bonded to the first substrate, wherein the plurality of exposed conductor layers are aligned and in contact with the surfaces of the exposed via plugs. A portion of the second surface of the first substrate is then removed to expose the opposite ends of the plurality of via plugs. A plurality of UBM layers is formed on the surfaces of the opposite ends of the plurality of via plugs. A plurality of solder bumps is formed and mounted on the UBM layers. A second substrate having a first surface and a second surface is provided, the solder bumps being mounted to the first surface of the second substrate. A plurality of solder balls is formed and mounted to the second surface of the second substrate. A third substrate is mounted to the solder balls.

摘要翻译： 提供一种制造半导体封装的方法。 在一个实施例中，提供其上具有多个暴露的导电层的半导体芯片。 提供具有第一表面和第二表面的第一基底，所述第一表面在其下具有多个暴露的通孔塞。 半导体芯片被接合到第一基板，其中多个暴露的导体层被对准并与暴露的通孔塞的表面接触。 然后去除第一基板的第二表面的一部分以暴露多个通孔塞的相对端。 在多个通孔塞的相对端的表面上形成多个UBM层。 多个焊料凸起形成并安装在UBM层上。 提供具有第一表面和第二表面的第二基底，焊料凸块安装到第二基底的第一表面。 多个焊球形成并安装在第二基板的第二表面上。 第三衬底安装到焊球。

公开(公告)号：US07846769B2

公开(公告)日：2010-12-07

申请号：US12639058

申请日：2009-12-16

申请人： Mirng-Ji Lii ,  Szu-Wei Lu ,  Tjandra Winata Karta ,  Chien-Hsiun Lee

发明人： Mirng-Ji Lii ,  Szu-Wei Lu ,  Tjandra Winata Karta ,  Chien-Hsiun Lee

IPC分类号： H01L21/44

CPC分类号： H01L21/563 ,  H01L23/295 ,  H01L23/3128 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01019 ,  H01L2924/01063 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014

摘要： A method includes joining an integrated circuit die having at least one low-k dielectric layer to a package substrate or printed circuit board using a plurality of solder bumps located between the die and the package substrate or printed circuit board. The low-k dielectric layer has a dielectric constant of about 3.0 or less. The solder bumps have a lead concentration of about 5% or less. A stratified underfill is formed between the die and the package substrate or printed circuit board.

摘要翻译： 一种方法包括使用位于管芯和封装衬底或印刷电路板之间的多个焊料凸块将具有至少一个低k​​电介质层的集成电路管芯连接到封装衬底或印刷电路板。 低k电介质层的介电常数约为3.0或更小。 焊锡凸块的铅浓度约为5％以下。 在模具和封装衬底或印刷电路板之间形成分层的底部填充物。

公开(公告)号：US07491624B2

公开(公告)日：2009-02-17

申请号：US11610752

申请日：2006-12-14

申请人： Szu-Wei Lu ,  Hsin-Hui Lee ,  Chien-Hsiun Lee ,  Mirng-Ji Lii

发明人： Szu-Wei Lu ,  Hsin-Hui Lee ,  Chien-Hsiun Lee ,  Mirng-Ji Lii

IPC分类号： H01L21/00 ,  H01L21/30 ,  H01L21/44

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L23/14 ,  H01L23/15 ,  H01L23/3735 ,  H01L2224/13116 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81805 ,  H01L2224/92125 ,  H01L2924/01019 ,  H01L2924/01037 ,  H01L2924/01068 ,  H01L2924/01322 ,  H05K1/0271 ,  H05K3/4602 ,  H05K2201/068 ,  H05K2201/10674

摘要： Disclosed are techniques that teach the replacement of the typical organic, plastic, or ceramic package substrate used in semiconductor package devices with a low-CTE package substrate. In one embodiment, a semiconductor device implementing the disclosed techniques is provided, where the device comprises an integrated circuit chip having at least one coupling component formed on an exterior surface thereof. Also, the device includes a package substrate having a mounting surface with bonding pads that are configured to receive the at least one coupling component. In such embodiments, the package substrate is selected or manufactured such that it has a coefficient of thermal expansion in a direction perpendicular to its mounting surface that is less than approximately twice a coefficient of thermal expansion along a plane parallel to its mounting surface.

摘要翻译： 公开的技术是教导用低CTE封装衬底替代半导体封装器件中典型的有机，塑料或陶瓷封装衬底的技术。 在一个实施例中，提供了实现所公开技术的半导体器件，其中该器件包括集成电路芯片，其具有形成在其外表面上的至少一个耦合部件。 而且，该装置还包括具有安装表面的封装基板，该安装表面具有用于接收至少一个耦合部件的焊盘。 在这样的实施例中，选择或制造封装衬底，使得其沿垂直于其安装表面的方向的热膨胀系数小于其平行于其安装表面的平面的热膨胀系数的大约两倍。

公开(公告)号：US07170159B1

公开(公告)日：2007-01-30

申请号：US11160753

申请日：2005-07-07

申请人： Szu-Wei Lu ,  Hsin-Hui Lee ,  Chien-Hsiun Lee ,  Mirng-Ji Lii

发明人： Szu-Wei Lu ,  Hsin-Hui Lee ,  Chien-Hsiun Lee ,  Mirng-Ji Lii

IPC分类号： H01L23/02

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L23/14 ,  H01L23/15 ,  H01L23/3735 ,  H01L2224/13116 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81805 ,  H01L2224/92125 ,  H01L2924/01019 ,  H01L2924/01037 ,  H01L2924/01068 ,  H01L2924/01322 ,  H05K1/0271 ,  H05K3/4602 ,  H05K2201/068 ,  H05K2201/10674

摘要： Disclosed are techniques that teach the replacement of the typical organic, plastic, or ceramic package substrate used in semiconductor package devices with a low-CTE package substrate. In one embodiment, a semiconductor device implementing the disclosed techniques is provided, where the device comprises an integrated circuit chip having at least one coupling component formed on an exterior surface thereof. Also, the device includes a package substrate having a mounting surface with bonding pads that are configured to receive the at least one coupling component. In such embodiments, the package substrate is selected or manufactured such that it has a coefficient of thermal expansion in a direction perpendicular to its mounting surface that is less than approximately twice a coefficient of thermal expansion along a plane parallel to its mounting surface.

摘要翻译： 公开的技术是教导用低CTE封装衬底替代半导体封装器件中典型的有机，塑料或陶瓷封装衬底的技术。 在一个实施例中，提供了实现所公开技术的半导体器件，其中该器件包括集成电路芯片，其具有形成在其外表面上的至少一个耦合部件。 而且，该装置还包括具有安装表面的封装基板，该安装表面具有用于接收至少一个耦合部件的焊盘。 在这样的实施例中，选择或制造封装衬底，使得其沿垂直于其安装表面的方向的热膨胀系数小于其平行于其安装表面的平面的热膨胀系数的大约两倍。

公开(公告)号：US20100093135A1

公开(公告)日：2010-04-15

申请号：US12639058

申请日：2009-12-16

申请人： Mirng-Ji Lii ,  Szu-Wei Lu ,  Tjandra Winata Karta ,  Chien-Hsiun Lee

发明人： Mirng-Ji Lii ,  Szu-Wei Lu ,  Tjandra Winata Karta ,  Chien-Hsiun Lee

IPC分类号： H01L21/56

CPC分类号： H01L21/563 ,  H01L23/295 ,  H01L23/3128 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01019 ,  H01L2924/01063 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014

摘要： A method includes joining an integrated circuit die having at least one low-k dielectric layer to a package substrate or printed circuit board using a plurality of solder bumps located between the die and the package substrate or printed circuit board. The low-k dielectric layer has a dielectric constant of about 3.0 or less. The solder bumps have a lead concentration of about 5% or less. A stratified underfill is formed between the die and the package substrate or printed circuit board.

摘要翻译： 一种方法包括使用位于管芯和封装衬底或印刷电路板之间的多个焊料凸块将具有至少一个低k​​电介质层的集成电路管芯连接到封装衬底或印刷电路板。 低k电介质层的介电常数约为3.0或更小。 焊锡凸块的铅浓度约为5％以下。 在模具和封装衬底或印刷电路板之间形成分层的底部填充物。

公开(公告)号：US20070087479A1

公开(公告)日：2007-04-19

申请号：US11610752

申请日：2006-12-14

申请人： Szu-Wei Lu ,  Hsin-Hui Lee ,  Chien-Hsiun Lee ,  Mirng-Ji Lii

发明人： Szu-Wei Lu ,  Hsin-Hui Lee ,  Chien-Hsiun Lee ,  Mirng-Ji Lii

IPC分类号： H01L21/00

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L23/14 ,  H01L23/15 ,  H01L23/3735 ,  H01L2224/13116 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81805 ,  H01L2224/92125 ,  H01L2924/01019 ,  H01L2924/01037 ,  H01L2924/01068 ,  H01L2924/01322 ,  H05K1/0271 ,  H05K3/4602 ,  H05K2201/068 ,  H05K2201/10674

摘要： Disclosed are techniques that teach the replacement of the typical organic, plastic, or ceramic package substrate used in semiconductor package devices with a low-CTE package substrate. In one embodiment, a semiconductor device implementing the disclosed techniques is provided, where the device comprises an integrated circuit chip having at least one coupling component formed on an exterior surface thereof. Also, the device includes a package substrate having a mounting surface with bonding pads that are configured to receive the at least one coupling component. In such embodiments, the package substrate is selected or manufactured such that it has a coefficient of thermal expansion in a direction perpendicular to its mounting surface that is less than approximately twice a coefficient of thermal expansion along a plane parallel to its mounting surface.

摘要翻译： 公开的技术是教导用低CTE封装衬底替代半导体封装器件中典型的有机，塑料或陶瓷封装衬底的技术。 在一个实施例中，提供了实现所公开技术的半导体器件，其中该器件包括集成电路芯片，其具有形成在其外表面上的至少一个耦合部件。 而且，该装置还包括具有安装表面的封装基板，该安装表面具有用于接收至少一个耦合部件的焊盘。 在这样的实施例中，选择或制造封装衬底，使得其沿垂直于其安装表面的方向的热膨胀系数小于其平行于其安装表面的平面的热膨胀系数的大约两倍。

公开(公告)号：US20070007649A1

公开(公告)日：2007-01-11

申请号：US11160753

申请日：2005-07-07

申请人： Szu-Wei Lu ,  Hsin-Hui Lee ,  Chien-Hsiun Lee ,  Mirng-Ji Lii

发明人： Szu-Wei Lu ,  Hsin-Hui Lee ,  Chien-Hsiun Lee ,  Mirng-Ji Lii

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L23/14 ,  H01L23/15 ,  H01L23/3735 ,  H01L2224/13116 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81805 ,  H01L2224/92125 ,  H01L2924/01019 ,  H01L2924/01037 ,  H01L2924/01068 ,  H01L2924/01322 ,  H05K1/0271 ,  H05K3/4602 ,  H05K2201/068 ,  H05K2201/10674

摘要： Disclosed are techniques that teach the replacement of the typical organic, plastic, or ceramic package substrate used in semiconductor package devices with a low-CTE package substrate. In one embodiment, a semiconductor device implementing the disclosed techniques is provided, where the device comprises an integrated circuit chip having at least one coupling component formed on an exterior surface thereof. Also, the device includes a package substrate having a mounting surface with bonding pads that are configured to receive the at least one coupling component. In such embodiments, the package substrate is selected or manufactured such that it has a coefficient of thermal expansion in a direction perpendicular to its mounting surface that is less than approximately twice a coefficient of thermal expansion along a plane parallel to its mounting surface.

摘要翻译： 公开的技术是教导用低CTE封装衬底替代半导体封装器件中典型的有机，塑料或陶瓷封装衬底的技术。 在一个实施例中，提供了实现所公开技术的半导体器件，其中该器件包括集成电路芯片，其具有形成在其外表面上的至少一个耦合部件。 而且，该装置还包括具有安装表面的封装基板，该安装表面具有用于接收至少一个耦合部件的焊盘。 在这样的实施例中，选择或制造封装衬底，使得其沿垂直于其安装表面的方向的热膨胀系数小于其平行于其安装表面的平面的热膨胀系数的大约两倍。

公开(公告)号：US08704383B2

公开(公告)日：2014-04-22

申请号：US13452562

申请日：2012-04-20

申请人： Szu-Wei Lu ,  Clinton Chao ,  Ann Luh ,  Tjandra Winata Karta ,  Jerry Tzou ,  Kuo-Chin Chang

发明人： Szu-Wei Lu ,  Clinton Chao ,  Ann Luh ,  Tjandra Winata Karta ,  Jerry Tzou ,  Kuo-Chin Chang

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/147 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5386 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/157 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/0401

摘要： A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 μm. A plurality of traces is formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. A semiconductor chip may be mounted on the solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips.

摘要翻译： 硅基薄封装衬底用于封装半导体芯片。 硅基薄封装基板优选具有小于约200μm的厚度。 在硅基薄封装衬底中形成多个迹线，连接BGA球和焊料凸块。 半导体芯片可以安装在焊料凸块上。 硅基薄封装衬底可以用作半导体芯片的载体。

公开(公告)号：US06596611B2

公开(公告)日：2003-07-22

申请号：US09846932

申请日：2001-05-01

申请人： Ming Lu ,  Szu-Wei Lu

发明人： Ming Lu ,  Szu-Wei Lu

IPC分类号： H01L21301

CPC分类号： H01L24/12 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： A method for forming wafer level package that has a serpentine-shaped electrode formed along a scribe line in-between two adjacent IC dies and the package formed are disclosed. In the method, each of the I/O redistribution lines connecting from an I/O redistribution pad is connected to a serpentine-shaped electrode for providing electrical communication during a subsequent electro-deposition process for forming a solder bump on the corresponding I/O redistribution pad. During a dicing operation of the wafer level package, a single cut through the center of the serpentine-shaped electrode can effect severance of all IC dies without possibility of any inter-die shorting or intra-die shorting.