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    ESD protection that supports LVDS and OCT
    1.
    发明授权
    ESD protection that supports LVDS and OCT 有权
    支持LVDS和OCT的ESD保护

    公开(公告)号：US07250660B1

    公开(公告)日：2007-07-31

    申请号：US10891988

    申请日：2004-07-14

    申请人： Cheng-Hsiung Huang ,  Chih-Ching Shih ,  Jeffrey Tyhach ,  Guu Lin ,  Chiakang Sung ,  Stephanie T. Tran

    发明人： Cheng-Hsiung Huang ,  Chih-Ching Shih ,  Jeffrey Tyhach ,  Guu Lin ,  Chiakang Sung ,  Stephanie T. Tran

    IPC分类号： H01L23/62 ,  H01L29/72 ,  H01L29/73 ,  H01L29/74 ,  H01L31/111

    CPC分类号： H01L27/0266

    摘要： Circuits are described that provide electrostatic discharge protection for I/O circuits that support the low voltage differential signaling (LVDS) and on-chip termination (OCT) standards. At least one additional transistor is connected across an I/O transistor. In the case of LVDS, a pair of stacked transistors is used in which the distance between the source/drain region and a well tap is considerably greater for the transistor connected to the I/O pad. A PMOS transistor and an NMOS transistor may also be connected in series between a first node such as a power supply node and the I/O pad. An OCT circuit is also disclosed in which the spacing between the source/drain region and a well tap in the OCT transistor is smaller than that in the I/O transistor.

    摘要翻译： 描述了为支持低电压差分信号（LVDS）和片上终止（OCT）标准的I / O电路提供静电放电保护的电路。 在I / O晶体管上连接至少一个附加晶体管。 在LVDS的情况下，使用一对堆叠的晶体管，其中源/漏区和阱抽头之间的距离对于连接到I / O焊盘的晶体管相当大。 PMOS晶体管和NMOS晶体管也可以串联连接在诸如电源节点的第一节点和I / O焊盘之间。 还公开了一种OCT电路，其中源极/漏极区域和OCT晶体管中的阱阱之间的间隔小于I / O晶体管中的间距。

    Electrostatic discharge protection circuit
    2.
    发明授权
    Electrostatic discharge protection circuit 有权
    静电放电保护电路

    公开(公告)号：US07400480B2

    公开(公告)日：2008-07-15

    申请号：US11890933

    申请日：2007-08-07

    申请人： Cheng-Hsiung Huang ,  Guu Lin ,  Shih-Lin S. Lee ,  Chih-Ching Shih ,  Irfan Rahim ,  Stephanie T. Tran

    发明人： Cheng-Hsiung Huang ,  Guu Lin ,  Shih-Lin S. Lee ,  Chih-Ching Shih ,  Irfan Rahim ,  Stephanie T. Tran

    IPC分类号： H02H3/22

    CPC分类号： H01L27/0266 ,  H01L27/0251

    摘要： Integrated circuits are provided that have sensitive circuitry such as programmable polysilicon fuses. Electrostatic discharge (ESD) protection circuitry is provided that prevents damage or undesired programming of the sensitive circuitry in the presence of an electrostatic discharge event. The electrostatic discharge protection circuitry may have a power ESD device that limits the voltage level across the sensitive circuitry to a maximum voltage and that draws current away from the sensitive circuitry when exposed to ESD signals. The electrostatic discharge protection circuitry may also have an ESD margin circuit that helps to prevent current flow through the sensitive circuitry when the maximum voltage is applied across the sensitive circuitry.

    摘要翻译： 提供具有诸如可编程多晶硅保险丝等敏感电路的集成电路。 提供静电放电（ESD）保护电路，防止在存在静电放电事件时敏感电路的损坏或不期望的编程。 静电放电保护电路可以具有电源ESD器件，其将敏感电路两端的电压电平限制到最大电压，并且当暴露于ESD信号时，其将电流从敏感电路吸取。 静电放电保护电路还可以具有ESD余量电路，当在敏感电路上施加最大电压时，该余量电路有助于防止电流流经敏感电路。

    Electrostatic discharge protection circuit
    4.
    发明申请
    Electrostatic discharge protection circuit 有权
    静电放电保护电路

    公开(公告)号：US20050270714A1

    公开(公告)日：2005-12-08

    申请号：US10861604

    申请日：2004-06-03

    申请人： Cheng-Hsiung Huang ,  Guu Lin ,  Shih-Lin Lee ,  Chih-Ching Shih ,  Irfan Rahim ,  Stephanie Tran

    发明人： Cheng-Hsiung Huang ,  Guu Lin ,  Shih-Lin Lee ,  Chih-Ching Shih ,  Irfan Rahim ,  Stephanie Tran

    IPC分类号： H01L27/02 ,  H02H9/00

    CPC分类号： H01L27/0266 ,  H01L27/0251

    摘要： Integrated circuits are provided that have sensitive circuitry such as programmable polysilicon fuses. Electrostatic discharge (ESD) protection circuitry is provided that prevents damage or undesired programming of the sensitive circuitry in the presence of an electrostatic discharge event. The electrostatic discharge protection circuitry may have a power ESD device that limits the voltage level across the sensitive circuitry to a maximum voltage and that draws current away from the sensitive circuitry when exposed to ESD signals. The electrostatic discharge protection circuitry may also have an ESD margin circuit that helps to prevent current flow through the sensitive circuitry when the maximum voltage is applied across the sensitive circuitry.

    摘要翻译： 提供具有诸如可编程多晶硅保险丝等敏感电路的集成电路。 提供静电放电（ESD）保护电路，防止在存在静电放电事件时敏感电路的损坏或不期望的编程。 静电放电保护电路可以具有电源ESD器件，其将敏感电路两端的电压电平限制到最大电压，并且当暴露于ESD信号时，其将电流从敏感电路吸取。 静电放电保护电路还可以具有ESD余量电路，当在敏感电路上施加最大电压时，该余量电路有助于防止电流流经敏感电路。

    Electrostatic discharge protection circuit
    5.
    发明申请
    Electrostatic discharge protection circuit 有权
    静电放电保护电路

    公开(公告)号：US20070279817A1

    公开(公告)日：2007-12-06

    申请号：US11890933

    申请日：2007-08-07

    申请人： Cheng-Hsiung Huang ,  Guu Lin ,  Shih-Lin Lee ,  Chih-Ching Shih ,  Irfan Rahim ,  Stephanie Tran

    发明人： Cheng-Hsiung Huang ,  Guu Lin ,  Shih-Lin Lee ,  Chih-Ching Shih ,  Irfan Rahim ,  Stephanie Tran

    IPC分类号： H02H9/00

    CPC分类号： H01L27/0266 ,  H01L27/0251

    摘要： Integrated circuits are provided that have sensitive circuitry such as programmable polysilicon fuses. Electrostatic discharge (ESD) protection circuitry is provided that prevents damage or undesired programming of the sensitive circuitry in the presence of an electrostatic discharge event. The electrostatic discharge protection circuitry may have a power ESD device that limits the voltage level across the sensitive circuitry to a maximum voltage and that draws current away from the sensitive circuitry when exposed to ESD signals. The electrostatic discharge protection circuitry may also have an ESD margin circuit that helps to prevent current flow through the sensitive circuitry when the maximum voltage is applied across the sensitive circuitry.

    摘要翻译： 提供具有诸如可编程多晶硅保险丝等敏感电路的集成电路。 提供静电放电（ESD）保护电路，防止在存在静电放电事件时敏感电路的损坏或不期望的编程。 静电放电保护电路可以具有电源ESD器件，其将敏感电路两端的电压电平限制到最大电压，并且当暴露于ESD信号时，其将电流从敏感电路吸取。 静电放电保护电路还可以具有ESD余量电路，当在敏感电路上施加最大电压时，该余量电路有助于防止电流流经敏感电路。

    Signal timing for I/O
    7.
    发明授权
    Signal timing for I/O 有权
    I / O信号时序

    公开(公告)号：US07317644B1

    公开(公告)日：2008-01-08

    申请号：US11303250

    申请日：2005-12-15

    申请人： Guu Lin ,  Stephanie T. Tran ,  Yen-Fu Lin

    发明人： Guu Lin ,  Stephanie T. Tran ,  Yen-Fu Lin

    IPC分类号： G11C7/00

    CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093

    摘要： Circuits, methods, and apparatus for ordering the timing of clock and data signals. Programmable delay cells are utilized in a data output cell to control a critical multiple data rate input/output write timing so the output can achieve better performance, such as higher maximum frequency of output (Fmax) performance. The delay cells ensure that critical timing criteria between clock signals and data high and low signals are satisfied so that there is a reduced chance of output glitching.

    摘要翻译： 用于排序时钟和数据信号时序的电路，方法和装置。 可编程延迟单元用于数据输出单元，以控制关键的多数据速率输入/输出写时序，以便输出可以实现更好的性能，例如更高的最大输出频率（Fmax）性能。 延迟单元确保了时钟信号和数据高和低信号之间的关键时序标准得到满足，从而减少了输出毛刺的几率。

    Flexible data strobe signal bus structure for wirebond and flip-chip packaging
    8.
    发明授权
    Flexible data strobe signal bus structure for wirebond and flip-chip packaging 有权
    灵活的数据选通信号总线结构，用于引线键合和倒装芯片封装

    公开(公告)号：US08385142B1

    公开(公告)日：2013-02-26

    申请号：US12464783

    申请日：2009-05-12

    申请人： Guu Lin ,  Yen-Fu Lin ,  Mark W. Fiester ,  Stephanie T. Tran

    发明人： Guu Lin ,  Yen-Fu Lin ,  Mark W. Fiester ,  Stephanie T. Tran

    IPC分类号： G11C5/06

    CPC分类号： G06F17/5054 ,  H01L2224/48091 ,  H01L2924/00014

    摘要： An integrated circuit with a flexible data strobe signal (DQS) bus structure is presented. The integrated circuit has a number of input/output (I/O) modules with a number of data pins to receive and transmit data. In addition, a subset of the I/O modules also have a data strobe pin. The input/output modules are connected to data strobe signal buses having a fixed configuration. The configuration of the fixed DQS bus groups a number of data pins with a corresponding data strobe pin and the grouping of data pin spans multiple I/O modules. The integrated circuit also has a flexible data bus connected to the I/O modules. Data pins of I/O modules of a second integrated circuit are mapped a subset of the data pins of corresponding I/O modules of the integrated circuit. The flexible data strobe signal bus enables selection of the subset of data pins in the integrated circuit.

    摘要翻译： 提出了一种具有灵活数据选通信号（DQS）总线结构的集成电路。 集成电路具有多个具有多个数据引脚的输入/输出（I / O）模块，用于接收和发送数据。 此外，I / O模块的一个子集还具有一个数据选通引脚。 输入/输出模块连接到具有固定配置的数据选通信号总线。 固定DQS总线的配置将多个具有相应数据选通引脚的数据引脚组合在一起，数据引脚分组跨多个I / O模块。 集成电路还具有连接到I / O模块的灵活数据总线。 将第二集成电路的I / O模块的数据引脚映射到集成电路的相应I / O模块的数据引脚的子集。 灵活的数据选通信号总线使得能够选择集成电路中的数据引脚子集。

    Flexible macrocell interconnect
    10.
    发明授权
    Flexible macrocell interconnect 失效
    灵活的宏单元互连

    公开(公告)号：US07161384B1

    公开(公告)日：2007-01-09

    申请号：US11180069

    申请日：2005-07-12

    申请人： Guu Lin ,  Stephanie Tran ,  Bruce Pederson ,  Brad Vest ,  Jim Park ,  Jay Schleicher

    发明人： Guu Lin ,  Stephanie Tran ,  Bruce Pederson ,  Brad Vest ,  Jim Park ,  Jay Schleicher

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17736

    摘要： Methods and apparatus for novel routing structures and methods that improve fitting of user-defined functions onto programmable logic devices. In particular, second time fitting is improved. Exemplary structures and methods include allowing product terms to be expanded using inputs from more than one neighboring macrocell by providing multiple expansion and bypassing paths. Also, product term OR shifting prevents macrocell output stages from being buried and made inaccessible, and macrocell outputs are provided on expander word lines, increasing efficiency of those lines, as well as conserving routing resources. Expansion, bypassing, OR shifting, and expander word lines may terminate at logic array block boundaries or may continue beyond these boundaries to other logic array blocks.

    摘要翻译： 用于新的路由结构和方法的方法和装置，其改善了用户定义的功能对可编程逻辑设备的拟合。 特别是第二次装配得到改善。 示例性结构和方法包括通过提供多个扩展和旁路路径允许使用来自多于一个相邻宏小区的输入扩展产品术语。 此外，产品术语“或”移位可防止宏单元输出级被掩埋并使其不可访问，并且在扩展器字线上提供宏单元输出，提高这些线路的效率以及节省路由资源。 扩展，旁路，或移位和扩展器字线可以以逻辑阵列块边界终止，或者可以超出这些边界到其他逻辑阵列块。