公开(公告)号：US06754105B1

公开(公告)日：2004-06-22

申请号：US10430582

申请日：2003-05-06

申请人： Chi Chang ,  Wei Zheng ,  Hidehiko Shiraiwa

发明人： Chi Chang ,  Wei Zheng ,  Hidehiko Shiraiwa

IPC分类号： G11C1604

CPC分类号： H01L27/11568 ,  G11C16/0475 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7887 ,  H01L29/7923

摘要： A memory device that includes a charge trapping region disposed laterally adjacent a first end of a channel such that energetic electrons traversing the channel can be ballistically injected into the charge trapping region.

摘要翻译： 一种存储器件，其包括电荷俘获区域，该电荷俘获区域设置成横向邻近沟道的第一端，使得穿过沟道的高能电子可以弹道地注入电荷俘获区域。

公开(公告)号：US06730564B1

公开(公告)日：2004-05-04

申请号：US10217821

申请日：2002-08-12

申请人： Mark T. Ramsbey ,  Yu Sun ,  Chi Chang ,  Hidehiko Shiraiwa

发明人： Mark T. Ramsbey ,  Yu Sun ,  Chi Chang ,  Hidehiko Shiraiwa

IPC分类号： H01L218247

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11534 ,  Y10S438/954

摘要： The present invention provides a process for saliciding word lines in a virtual ground array flash memory device without causing shorting between bit lines. According to one aspect of the invention, saliciding takes place prior to patterning one or more layers of a memory cell stack. The unpatterned layers protect the substrate between word lines from becoming salicided. The invention provides virtual ground array flash memory devices with doped and salicided word lines, but no shorting between bit lines, even in virtual ground arrays where there are no oxide island isolation regions between word lines. Potential advantages of such structures include reduced size, reduced number of processing steps, and reduced exposure to high temperature cycling.

摘要翻译： 本发明提供了一种在虚拟接地阵列闪存器件中对字线进行水印处理，而不引起位线之间的短路。 根据本发明的一个方面，在对存储单元堆叠的一层或多层进行构图之前进行水化。 未图案化的层保护字线之间的基板不会变成水银。 本发明提供具有掺杂和含水字线的虚拟接地阵列闪存器件，但是即使在字线之间没有氧化物岛隔离区域的虚拟接地阵列中也不会在位线之间发生短路。 这种结构的潜在优点包括减小的尺寸，减少的加工步骤数量以及降低暴露于高温循环。

公开(公告)号：US07671403B2

公开(公告)日：2010-03-02

申请号：US11567257

申请日：2006-12-06

申请人： Wei Zheng ,  Chi Chang ,  Mark Randolph ,  Satoshi Torii

发明人： Wei Zheng ,  Chi Chang ,  Mark Randolph ,  Satoshi Torii

IPC分类号： H01L29/792

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： A device includes a substrate and multiple wells formed over the substrate and isolated from one another by dielectric trenches. The device further includes multiple memory elements formed over the wells, each of the memory elements extending approximately perpendicular to the wells and including a material doped with n-type impurities. The device also includes multiple source/drain regions, each source/drain region formed within one of multiple trenches and inside one of the plurality of wells between a pair of the memory elements, each of the source/drain regions implanted with p-type impurities. The device further includes a first substrate contact formed in a first one of the multiple trenches through a first one of the wells into the substrate and a second substrate contact formed in a second one of the multiple trenches through a second one of the wells into the substrate.

摘要翻译： 一种器件包括衬底和形成在衬底上并由电介质沟槽彼此隔离的多个阱。 该器件还包括形成在阱上的多个存储元件，每个存储元件大致垂直于阱延伸并且包括掺杂有n型杂质的材料。 器件还包括多个源极/漏极区域，每个源极/漏极区域形成在多个沟槽中的一个内，并且在一对存储元件之间的多个阱中的一个内部，源极/漏极区域中的每一个注入p型杂质 。 所述器件还包括形成在所述多个沟槽中的第一个沟槽中的第一衬底接触件，穿过所述衬底中的第一孔，以及形成在所述多个沟槽中的第二个沟槽中的第二衬底接触件中的第二衬底接触入第 基质。

公开(公告)号：US20080142875A1

公开(公告)日：2008-06-19

申请号：US11639666

申请日：2006-12-15

申请人： Chungho Lee ,  Wei Zheng ,  Chi Chang ,  Unsoon Kim ,  Hiroyuki Kinoshita

发明人： Chungho Lee ,  Wei Zheng ,  Chi Chang ,  Unsoon Kim ,  Hiroyuki Kinoshita

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/1037 ,  H01L29/1083 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/66537 ,  H01L29/7887 ,  H01L29/7923

摘要： Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes are disclosed. A disclosed method includes forming a first trench and an adjacent second trench in a semiconductor substrate, the first trench and the second trench each defining a first sidewall and a second sidewall respectively and forming a first source/drain region in the substrate and a second source/drain region in the substrate, where the first source/drain region and the second source/drain region are formed substantially under the first trench and the second trench in the semiconductor substrate respectively. Moreover, a method includes forming a bit line punch through barrier in the substrate between the first source/drain region and the second source drain region and forming a first storage element on the first sidewall of the first trench and a second storage element on the second sidewall of the second element. A word line is formed in contact with the first storage element and the second storage element.

摘要翻译： 公开了具有分割电荷存储节点的存储单元和用于制造具有分离电荷存储节点的存储单元的方法。 所公开的方法包括在半导体衬底中形成第一沟槽和相邻的第二沟槽，第一沟槽和第二沟槽分别限定第一侧壁和第二侧壁，并在衬底中形成第一源极/漏极区域，第二源极 /漏极区域，其中第一源极/漏极区域和第二源极/漏极区域分别基本上形成在半导体衬底中的第一沟槽和第二沟槽下方。 此外，一种方法包括在第一源极/漏极区域和第二源极漏极区域之间的衬底中形成位线穿通阻挡层，并在第一沟槽的第一侧壁上形成第一存储元件，在第二沟槽的第二沟槽上形成第二存储元件 第二元件的侧壁。 形成与第一存储元件和第二存储元件接触的字线。

公开(公告)号：US20080135918A1

公开(公告)日：2008-06-12

申请号：US11567257

申请日：2006-12-06

申请人： Wei Zheng ,  Chi Chang ,  Mark Randolph ,  Satoshi Torii

发明人： Wei Zheng ,  Chi Chang ,  Mark Randolph ,  Satoshi Torii

IPC分类号： H01L27/115

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： A device includes a substrate and multiple wells formed over the substrate and isolated from one another by dielectric trenches. The device further includes multiple memory elements formed over the wells, each of the memory elements extending approximately perpendicular to the wells and including a material doped with n-type impurities. The device also includes multiple source/drain regions, each source/drain region formed within one of multiple trenches and inside one of the plurality of wells between a pair of the memory elements, each of the source/drain regions implanted with p-type impurities. The device further includes a first substrate contact formed in a first one of the multiple trenches through a first one of the wells into the substrate and a second substrate contact formed in a second one of the multiple trenches through a second one of the wells into the substrate.

摘要翻译： 一种器件包括衬底和形成在衬底上并由电介质沟槽彼此隔离的多个阱。 该器件还包括形成在阱上的多个存储元件，每个存储元件大致垂直于阱延伸并且包括掺杂有n型杂质的材料。 器件还包括多个源极/漏极区域，每个源极/漏极区域形成在多个沟槽中的一个内，并且在一对存储元件之间的多个阱中的一个内部，源极/漏极区域中的每一个注入p型杂质 。 所述器件还包括形成在所述多个沟槽中的第一个沟槽中的第一衬底接触件，穿过所述衬底中的第一孔，以及形成在所述多个沟槽中的第二个沟槽中的第二衬底接触件中的第二衬底接触入第 基质。

公开(公告)号：US06906959B2

公开(公告)日：2005-06-14

申请号：US10306252

申请日：2002-11-27

申请人： Mark W. Randolph ,  Chi Chang ,  Yi He ,  Wei Zheng ,  Edward F. Runnion ,  Zhizheng Liu

发明人： Mark W. Randolph ,  Chi Chang ,  Yi He ,  Wei Zheng ,  Edward F. Runnion ,  Zhizheng Liu

IPC分类号： G11C16/04 ,  G11C16/14 ,  H01L21/336 ,  H01L29/792

CPC分类号： H01L29/66833 ,  G11C16/0475 ,  G11C16/14 ,  H01L29/7923

摘要： The present invention is a method and system for erasing a nitride memory device. In one embodiment of the present invention, an isolated P-well is formed in a semiconductor substrate. A plurality of N-type impurity concentrations are formed in the isolated P-well and a nitride memory cell is fabricated between two of the N-type impurity concentrations. Finally, an electrical contact is coupled to the isolated P-well.

摘要翻译： 本发明是一种擦除氮化物存储器件的方法和系统。 在本发明的一个实施例中，在半导体衬底中形成隔离的P阱。 在分离的P阱中形成多个N型杂质浓度，并且在两种N型杂质浓度之间制造氮化物存储单元。 最后，电接点耦合到隔离的P阱。

公开(公告)号：US08742486B2

公开(公告)日：2014-06-03

申请号：US11702846

申请日：2007-02-05

申请人： Wei Zheng ,  Chi Chang ,  Unsoon Kim

发明人： Wei Zheng ,  Chi Chang ,  Unsoon Kim

IPC分类号： H01L29/68

CPC分类号： H01L29/792 ,  H01L21/823418 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/7923

摘要： An embodiment of the present invention is directed to a memory cell. The memory cell includes a first trench formed in a semiconductor substrate and a second trench formed in said semiconductor substrate adjacent to said first trench. The first trench and the second trench each define a first side wall and a second sidewall respectively. The memory cell further includes a first storage element formed on the first sidewall of the first trench and a second storage element formed on the second sidewall of the second trench.

摘要翻译： 本发明的实施例涉及存储单元。 存储单元包括形成在半导体衬底中的第一沟槽和形成在与所述第一沟槽相邻的所述半导体衬底中的第二沟槽。 第一沟槽和第二沟槽分别限定第一侧壁和第二侧壁。 存储单元还包括形成在第一沟槽的第一侧壁上的第一存储元件和形成在第二沟槽的第二侧壁上的第二存储元件。

公开(公告)号：US08076712B2

公开(公告)日：2011-12-13

申请号：US12840165

申请日：2010-07-20

申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

IPC分类号： H01L29/788

CPC分类号： H01L29/42332 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/7887 ,  H01L29/7923

摘要： A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.

摘要翻译： 提供了双电荷存储节点存储器件及其制造方法。 在一个实施例中，形成包括凹入半导体衬底的第一部分和在衬底上延伸的第二部分的电介质插塞。 在第二部分上形成一层半导体材料。 第一层状结构形成在电介质塞的第二部分的第一侧上，并且第二层结构形成在第二侧上，每个层叠结构覆盖在半导体材料层上，并且包括第一和第二层之间的电荷存储层 和第二电介质层。 将离子注入到衬底中以形成第一位线和第二位线，并且沉积和图案化导电材料层以形成覆盖在电介质插塞和第一和第二分层结构上的控制栅极。

公开(公告)号：US07767517B2

公开(公告)日：2010-08-03

申请号：US11613513

申请日：2006-12-20

申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

IPC分类号： H01L21/8242

CPC分类号： H01L29/42332 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/7887 ,  H01L29/7923

摘要： A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.

摘要翻译： 提供了双电荷存储节点存储器件及其制造方法。 在一个实施例中，形成包括凹入半导体衬底的第一部分和在衬底上延伸的第二部分的电介质插塞。 在第二部分上形成一层半导体材料。 第一层状结构形成在电介质塞的第二部分的第一侧上，并且形成在第二侧上的第二层状结构，每个层叠结构覆盖在半导体材料层上，并且包括第一和第二层之间的电荷存储层 和第二电介质层。 将离子注入到衬底中以形成第一位线和第二位线，并且沉积和图案化导电材料层以形成覆盖在电介质插塞和第一和第二分层结构上的控制栅极。

公开(公告)号：US20080149999A1

公开(公告)日：2008-06-26

申请号：US11613513

申请日：2006-12-20

申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/42332 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/7887 ,  H01L29/7923

摘要： A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.

摘要翻译： 提供了双电荷存储节点存储器件及其制造方法。 在一个实施例中，形成包括凹入半导体衬底的第一部分和在衬底上延伸的第二部分的电介质插塞。 在第二部分上形成一层半导体材料。 第一层状结构形成在电介质塞的第二部分的第一侧上，并且形成在第二侧上的第二层状结构，每个层叠结构覆盖在半导体材料层上，并且包括第一和第二层之间的电荷存储层 和第二电介质层。 将离子注入到衬底中以形成第一位线和第二位线，并且沉积和图案化导电材料层以形成覆盖在电介质插塞和第一和第二分层结构上的控制栅极。