公开(公告)号：US09159568B2

公开(公告)日：2015-10-13

申请号：US11639666

申请日：2006-12-15

申请人： Chungho Lee ,  Wei Zheng ,  Chi Chang ,  Unsoon Kim ,  Hiroyuki Kinoshita

发明人： Chungho Lee ,  Wei Zheng ,  Chi Chang ,  Unsoon Kim ,  Hiroyuki Kinoshita

IPC分类号： H01L21/28 ,  H01L29/66 ,  H01L29/10 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/1037 ,  H01L29/1083 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/66537 ,  H01L29/7887 ,  H01L29/7923

摘要： Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes are disclosed. A disclosed method includes forming a first trench and an adjacent second trench in a semiconductor substrate, the first trench and the second trench each defining a first sidewall and a second sidewall respectively and forming a first source/drain region in the substrate and a second source/drain region in the substrate, where the first source/drain region and the second source/drain region are formed substantially under the first trench and the second trench in the semiconductor substrate respectively. Moreover, a method includes forming a bit line punch through barrier in the substrate between the first source/drain region and the second source drain region and forming a first storage element on the first sidewall of the first trench and a second storage element on the second sidewall of the second element. A word line is formed in contact with the first storage element and the second storage element.

摘要翻译： 公开了具有分割电荷存储节点的存储单元和用于制造具有分离电荷存储节点的存储单元的方法。 所公开的方法包括在半导体衬底中形成第一沟槽和相邻的第二沟槽，第一沟槽和第二沟槽分别限定第一侧壁和第二侧壁，并在衬底中形成第一源极/漏极区域，第二源极 /漏极区域，其中第一源极/漏极区域和第二源极/漏极区域分别基本上形成在半导体衬底中的第一沟槽和第二沟槽下方。 此外，一种方法包括在第一源极/漏极区域和第二源极漏极区域之间的衬底中形成位线穿通阻挡层，并在第一沟槽的第一侧壁上形成第一存储元件，在第二沟槽的第二沟槽上形成第二存储元件 第二元件的侧壁。 形成与第一存储元件和第二存储元件接触的字线。

公开(公告)号：US20080142875A1

公开(公告)日：2008-06-19

申请号：US11639666

申请日：2006-12-15

申请人： Chungho Lee ,  Wei Zheng ,  Chi Chang ,  Unsoon Kim ,  Hiroyuki Kinoshita

发明人： Chungho Lee ,  Wei Zheng ,  Chi Chang ,  Unsoon Kim ,  Hiroyuki Kinoshita

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/1037 ,  H01L29/1083 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/66537 ,  H01L29/7887 ,  H01L29/7923

摘要： Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes are disclosed. A disclosed method includes forming a first trench and an adjacent second trench in a semiconductor substrate, the first trench and the second trench each defining a first sidewall and a second sidewall respectively and forming a first source/drain region in the substrate and a second source/drain region in the substrate, where the first source/drain region and the second source/drain region are formed substantially under the first trench and the second trench in the semiconductor substrate respectively. Moreover, a method includes forming a bit line punch through barrier in the substrate between the first source/drain region and the second source drain region and forming a first storage element on the first sidewall of the first trench and a second storage element on the second sidewall of the second element. A word line is formed in contact with the first storage element and the second storage element.

摘要翻译： 公开了具有分割电荷存储节点的存储单元和用于制造具有分离电荷存储节点的存储单元的方法。 所公开的方法包括在半导体衬底中形成第一沟槽和相邻的第二沟槽，第一沟槽和第二沟槽分别限定第一侧壁和第二侧壁，并在衬底中形成第一源极/漏极区域，第二源极 /漏极区域，其中第一源极/漏极区域和第二源极/漏极区域分别基本上形成在半导体衬底中的第一沟槽和第二沟槽下方。 此外，一种方法包括在第一源极/漏极区域和第二源极漏极区域之间的衬底中形成位线穿通阻挡层，并在第一沟槽的第一侧壁上形成第一存储元件，在第二沟槽的第二沟槽上形成第二存储元件 第二元件的侧壁。 形成与第一存储元件和第二存储元件接触的字线。

公开(公告)号：US08076712B2

公开(公告)日：2011-12-13

申请号：US12840165

申请日：2010-07-20

申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

IPC分类号： H01L29/788

CPC分类号： H01L29/42332 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/7887 ,  H01L29/7923

摘要： A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.

摘要翻译： 提供了双电荷存储节点存储器件及其制造方法。 在一个实施例中，形成包括凹入半导体衬底的第一部分和在衬底上延伸的第二部分的电介质插塞。 在第二部分上形成一层半导体材料。 第一层状结构形成在电介质塞的第二部分的第一侧上，并且第二层结构形成在第二侧上，每个层叠结构覆盖在半导体材料层上，并且包括第一和第二层之间的电荷存储层 和第二电介质层。 将离子注入到衬底中以形成第一位线和第二位线，并且沉积和图案化导电材料层以形成覆盖在电介质插塞和第一和第二分层结构上的控制栅极。

公开(公告)号：US07767517B2

公开(公告)日：2010-08-03

申请号：US11613513

申请日：2006-12-20

申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

IPC分类号： H01L21/8242

CPC分类号： H01L29/42332 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/7887 ,  H01L29/7923

摘要： A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.

摘要翻译： 提供了双电荷存储节点存储器件及其制造方法。 在一个实施例中，形成包括凹入半导体衬底的第一部分和在衬底上延伸的第二部分的电介质插塞。 在第二部分上形成一层半导体材料。 第一层状结构形成在电介质塞的第二部分的第一侧上，并且形成在第二侧上的第二层状结构，每个层叠结构覆盖在半导体材料层上，并且包括第一和第二层之间的电荷存储层 和第二电介质层。 将离子注入到衬底中以形成第一位线和第二位线，并且沉积和图案化导电材料层以形成覆盖在电介质插塞和第一和第二分层结构上的控制栅极。

公开(公告)号：US20080149999A1

公开(公告)日：2008-06-26

申请号：US11613513

申请日：2006-12-20

申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/42332 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/7887 ,  H01L29/7923

摘要： A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.

摘要翻译： 提供了双电荷存储节点存储器件及其制造方法。 在一个实施例中，形成包括凹入半导体衬底的第一部分和在衬底上延伸的第二部分的电介质插塞。 在第二部分上形成一层半导体材料。 第一层状结构形成在电介质塞的第二部分的第一侧上，并且形成在第二侧上的第二层状结构，每个层叠结构覆盖在半导体材料层上，并且包括第一和第二层之间的电荷存储层 和第二电介质层。 将离子注入到衬底中以形成第一位线和第二位线，并且沉积和图案化导电材料层以形成覆盖在电介质插塞和第一和第二分层结构上的控制栅极。

公开(公告)号：US07785965B2

公开(公告)日：2010-08-31

申请号：US11530145

申请日：2006-09-08

申请人： Unsoon Kim ,  Kyunghoon Min ,  Ning Cheng ,  Hiroyuki Kinoshita ,  Sugino Rinji ,  Timothy Thurgate ,  Angela Hui ,  Jihwan Choi ,  Chi Chang

发明人： Unsoon Kim ,  Kyunghoon Min ,  Ning Cheng ,  Hiroyuki Kinoshita ,  Sugino Rinji ,  Timothy Thurgate ,  Angela Hui ,  Jihwan Choi ,  Chi Chang

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11568 ,  H01L29/42352 ,  H01L29/7923

摘要： Dual storage node memory devices and methods for fabricating dual storage node memory devices have been provided. In accordance with an exemplary embodiment, a method includes the steps of etching a plurality of trenches in a semiconductor substrate and forming a layered structure within the trenches. The layered structure includes a tunnel dielectric layer and a charge storage layer. Bit lines are formed within the semiconductor substrate and a layer of conductive material is deposited overlying the layered structure.

摘要翻译： 已经提供了双存储节点存储器件和用于制造双存储节点存储器件的方法。 根据示例性实施例，一种方法包括以下步骤：蚀刻半导体衬底中的多个沟槽并在沟槽内形成分层结构。 层状结构包括隧道介电层和电荷存储层。 位线形成在半导体衬底内，并且一层导电材料沉积在层叠结构之上。

公开(公告)号：US20080064165A1

公开(公告)日：2008-03-13

申请号：US11530145

申请日：2006-09-08

申请人： Unsoon Kim ,  Kyunghoon Min ,  Ning Cheng ,  Hiroyuki Kinoshita ,  Sugino Rinji ,  Timothy Thurgate ,  Angela Hui ,  Jihwan Choi ,  Chi Chang

发明人： Unsoon Kim ,  Kyunghoon Min ,  Ning Cheng ,  Hiroyuki Kinoshita ,  Sugino Rinji ,  Timothy Thurgate ,  Angela Hui ,  Jihwan Choi ,  Chi Chang

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11568 ,  H01L29/42352 ,  H01L29/7923

摘要： Dual storage node memory devices and methods for fabricating dual storage node memory devices have been provided. In accordance with an exemplary embodiment, a method includes the steps of etching a plurality of trenches in a semiconductor substrate and forming a layered structure within the trenches. The layered structure includes a tunnel dielectric layer and a charge storage layer. Bit lines are formed within the semiconductor substrate and a layer of conductive material is deposited overlying the layered structure.

摘要翻译： 已经提供了双存储节点存储器件和用于制造双存储节点存储器件的方法。 根据示例性实施例，一种方法包括以下步骤：蚀刻半导体衬底中的多个沟槽并在沟槽内形成分层结构。 层状结构包括隧道介电层和电荷存储层。 位线形成在半导体衬底内，并且一层导电材料沉积在层叠结构之上。

公开(公告)号：US08742486B2

公开(公告)日：2014-06-03

申请号：US11702846

申请日：2007-02-05

申请人： Wei Zheng ,  Chi Chang ,  Unsoon Kim

发明人： Wei Zheng ,  Chi Chang ,  Unsoon Kim

IPC分类号： H01L29/68

CPC分类号： H01L29/792 ,  H01L21/823418 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/7923

摘要： An embodiment of the present invention is directed to a memory cell. The memory cell includes a first trench formed in a semiconductor substrate and a second trench formed in said semiconductor substrate adjacent to said first trench. The first trench and the second trench each define a first side wall and a second sidewall respectively. The memory cell further includes a first storage element formed on the first sidewall of the first trench and a second storage element formed on the second sidewall of the second trench.

摘要翻译： 本发明的实施例涉及存储单元。 存储单元包括形成在半导体衬底中的第一沟槽和形成在与所述第一沟槽相邻的所述半导体衬底中的第二沟槽。 第一沟槽和第二沟槽分别限定第一侧壁和第二侧壁。 存储单元还包括形成在第一沟槽的第一侧壁上的第一存储元件和形成在第二沟槽的第二侧壁上的第二存储元件。

公开(公告)号：US20070205455A1

公开(公告)日：2007-09-06

申请号：US11702846

申请日：2007-02-05

申请人： Wei Zheng ,  Chi Chang ,  Unsoon Kim

发明人： Wei Zheng ,  Chi Chang ,  Unsoon Kim

IPC分类号： H01L29/76

CPC分类号： H01L29/792 ,  H01L21/823418 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/7923

摘要： An embodiment of the present invention is directed to a memory cell. The memory cell includes a first trench formed in a semiconductor substrate and a second trench formed in said semiconductor substrate adjacent to said first trench. The first trench and the second trench each define a first side wall and a second sidewall respectively. The memory cell further includes a first storage element formed on the first sidewall of the first trench and a second storage element formed on the second sidewall of the second trench.

摘要翻译： 本发明的实施例涉及存储单元。 存储单元包括形成在半导体衬底中的第一沟槽和形成在与所述第一沟槽相邻的所述半导体衬底中的第二沟槽。 第一沟槽和第二沟槽分别限定第一侧壁和第二侧壁。 存储单元还包括形成在第一沟槽的第一侧壁上的第一存储元件和形成在第二沟槽的第二侧壁上的第二存储元件。

公开(公告)号：US07307002B2

公开(公告)日：2007-12-11

申请号：US11099339

申请日：2005-04-04

申请人： Unsoon Kim ,  Hiroyuki Kinoshita ,  Yu Sun ,  Krishnashree Achuthan ,  Christopher H. Raeder ,  Christopher M. Foster ,  Harpreet Kaur Sachar ,  Kashmir Singh Sahota

发明人： Unsoon Kim ,  Hiroyuki Kinoshita ,  Yu Sun ,  Krishnashree Achuthan ,  Christopher H. Raeder ,  Christopher M. Foster ,  Harpreet Kaur Sachar ,  Kashmir Singh Sahota

IPC分类号： H01L21/76

CPC分类号： H01L27/105 ,  H01L21/3212 ,  H01L21/32139 ,  H01L21/76229 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11543 ,  H01L27/11568

摘要： A method is disclosed for the definition of the poly-1 layer in a semiconductor wafer. A non-critical mask is used to recess field oxides in the periphery prior to poly-1 deposition by an amount equal to the final poly-1 thickness. A complimentary non-critical mask is used to permit CMP of the core to expose the tops of core oxide mesas from the shallow isolation trenches.

摘要翻译： 公开了一种用于在半导体晶片中定义多晶硅层的方法。 使用非临界掩模在聚-1沉积之前将外围的场氧化物凹入等于最终聚-1厚度的量。 使用互补的非关键掩模来允许芯的CMP将浅层隔离沟的核心氧化物台面的顶部暴露出来。