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    Flash memory device and related erase operation
    1.
    发明授权
    Flash memory device and related erase operation 有权
    闪存设备和相关擦除操作

    公开(公告)号：US07433244B2

    公开(公告)日：2008-10-07

    申请号：US11501070

    申请日：2006-08-09

    申请人： Chi-Weon Yoon ,  Heung-Soo Lim

    发明人： Chi-Weon Yoon ,  Heung-Soo Lim

    IPC分类号： G11C16/00

    CPC分类号： G11C16/16 ,  G11C16/3409 ,  G11C16/345 ,  G11C16/3477

    摘要： An erase operation for a flash memory device includes identifying a sector group including a plurality of sectors based on an address, simultaneously pre-programming the sectors in the sector group, simultaneously erasing the sectors the sector group, and simultaneously post-programming the sectors in the sector group.

    摘要翻译： 闪存器件的擦除操作包括基于地址识别包括多个扇区的扇区组，同时对扇区组中的扇区进行预编程，同时擦除扇区组，并同时对扇区进行后编程 行业组。

    Flash memory device having a data buffer and programming method of the same
    2.
    发明授权
    Flash memory device having a data buffer and programming method of the same 有权
    具有数据缓冲器的闪存器件及其编程方法

    公开(公告)号：US07539077B2

    公开(公告)日：2009-05-26

    申请号：US11775872

    申请日：2007-07-11

    申请人： Chi-Weon Yoon ,  Heung-Soo Lim

    发明人： Chi-Weon Yoon ,  Heung-Soo Lim

    IPC分类号： G11C8/00

    CPC分类号： G11C7/1078 ,  G11C7/1087 ,  G11C7/1096 ,  G11C16/06

    摘要： A flash memory device includes a memory cell array with multiple memory cells, a data buffer, a write driver and a controller. The data buffer stores data to be programmed into the memory cells, the data having sequential data addresses. The write driver programs the data stored in the data buffer into the memory cells during one programming operation. The controller controls operations of the data buffer and the write driver, and performs flexible mapping between addresses of the data buffer and the data addresses based on a first address of the data.

    摘要翻译： 闪存器件包括具有多个存储器单元的存储单元阵列，数据缓冲器，写入驱动器和控制器。 数据缓冲器将要编程的数据存储到存储器单元中，数据具有顺序数据地址。 写入驱动器在一个编程操作期间将存储在数据缓冲器中的数据编程到存储器单元中。 控制器控制数据缓冲器和写入驱动器的操作，并且基于数据的第一地址在数据缓冲器的地址和数据地址之间执行灵活的映射。

    Semiconductor memory device using pipelined-buffer programming and related method
    3.
    发明授权
    Semiconductor memory device using pipelined-buffer programming and related method 失效
    半导体存储器件采用流水线缓冲编程及相关方法

    公开(公告)号：US07599222B2

    公开(公告)日：2009-10-06

    申请号：US11520665

    申请日：2006-09-14

    申请人： Chi-Weon Yoon ,  Heung-Soo Lim

    发明人： Chi-Weon Yoon ,  Heung-Soo Lim

    IPC分类号： G11C11/34

    CPC分类号： G11C16/10 ,  G11C16/26 ,  G11C16/3454 ,  G11C2216/14

    摘要： Disclosed is a semiconductor memory device which is operable a pipelined-buffer programming and includes a cell array including a plurality of memory cells, a write driver circuit divided into a plurality of write units, each write unit programming memory cells with a first data, a sense amplifier circuit divided into plurality of read units of the same number as the plurality of write units, each read unit sensing bit lines of the cell array during a program verify operation, a selection circuit for selecting one of the write units and one of the read units in response to a column address and a data input circuit for providing the first data to the selected write unit during a program operation and for receiving verifying data from the selected read unit during the program verify operation.

    摘要翻译： 公开了一种半导体存储器件，其可操作流水线缓冲器编程，并且包括包括多个存储器单元的单元阵列，分成多个写单元的写驱动器电路，每个写单元编程存储单元与第一数据， 读取放大器电路被划分为与多个写入单元相同数量的读取单元，每个读取单元在程序验证操作期间感测单元阵列的位线，用于选择写入单元之一的选择电路和 响应于列地址读取单元和数据输入电路，用于在编程操作期间将所述第一数据提供给所选择的写入单元，并且用于在所述程序验证操作期间从所选择的读取单元接收验证数据。

    FLASH MEMORY DEVICE HAVING A DATA BUFFER AND PROGRAMMING METHOD OF THE SAME
    4.
    发明申请
    FLASH MEMORY DEVICE HAVING A DATA BUFFER AND PROGRAMMING METHOD OF THE SAME 有权
    具有数据缓冲器的闪存存储器件及其编程方法

    公开(公告)号：US20080031050A1

    公开(公告)日：2008-02-07

    申请号：US11775872

    申请日：2007-07-11

    申请人： Chi-Weon Yoon ,  Heung-Soo Lim

    发明人： Chi-Weon Yoon ,  Heung-Soo Lim

    IPC分类号： G11C16/04 ,  G11C7/10

    CPC分类号： G11C7/1078 ,  G11C7/1087 ,  G11C7/1096 ,  G11C16/06

    摘要： A flash memory device includes a memory cell array with multiple memory cells, a data buffer, a write driver and a controller. The data buffer stores data to be programmed into the memory cells, the data having sequential data addresses. The write driver programs the data stored in the data buffer into the memory cells during one programming operation. The controller controls operations of the data buffer and the write driver, and performs flexible mapping between addresses of the data buffer and the data addresses based on a first address of the data.

    摘要翻译： 闪存器件包括具有多个存储器单元的存储单元阵列，数据缓冲器，写入驱动器和控制器。 数据缓冲器将要编程的数据存储到存储器单元中，数据具有顺序数据地址。 写入驱动器在一个编程操作期间将存储在数据缓冲器中的数据编程到存储器单元中。 控制器控制数据缓冲器和写入驱动器的操作，并且基于数据的第一地址在数据缓冲器的地址和数据地址之间执行灵活的映射。

    Semiconductor memory device using pipelined-buffer programming and related method
    5.
    发明申请
    Semiconductor memory device using pipelined-buffer programming and related method 失效
    半导体存储器件采用流水线缓冲编程及相关方法

    公开(公告)号：US20070150646A1

    公开(公告)日：2007-06-28

    申请号：US11520665

    申请日：2006-09-14

    申请人： Chi-Weon Yoon ,  Heung-Soo Lim

    发明人： Chi-Weon Yoon ,  Heung-Soo Lim

    IPC分类号： G06F12/00

    CPC分类号： G11C16/10 ,  G11C16/26 ,  G11C16/3454 ,  G11C2216/14

    摘要： Disclosed is a semiconductor memory device which is operable a pipelined-buffer programming and includes a cell array including a plurality of memory cells, a write driver circuit divided into a plurality of write units, each write unit programming memory cells with a first data, a sense amplifier circuit divided into plurality of read units of the same number as the plurality of write units, each read unit sensing bit lines of the cell array during a program verify operation, a selection circuit for selecting one of the write units and one of the read units in response to a column address and a data input circuit for providing the first data to the selected write unit during a program operation and for receiving verifying data from the selected read unit during the program verify operation.

    摘要翻译： 公开了一种半导体存储器件，其可操作流水线缓冲器编程，并且包括包括多个存储器单元的单元阵列，分成多个写单元的写驱动器电路，每个写单元编程存储单元与第一数据， 读取放大器电路被划分为与多个写入单元相同数量的读取单元，每个读取单元在程序验证操作期间感测单元阵列的位线，用于选择写入单元之一的选择电路和 响应于列地址读取单元和数据输入电路，用于在编程操作期间将所述第一数据提供给所选择的写入单元，并且用于在所述程序验证操作期间从所选择的读取单元接收验证数据。

    Flash memory device and related erase operation
    6.
    发明申请
    Flash memory device and related erase operation 有权
    闪存设备和相关擦除操作

    公开(公告)号：US20070147136A1

    公开(公告)日：2007-06-28

    申请号：US11501070

    申请日：2006-08-09

    申请人： Chi-Weon Yoon ,  Heung-Soo Lim

    发明人： Chi-Weon Yoon ,  Heung-Soo Lim

    IPC分类号： G11C16/04 ,  G11C11/34

    CPC分类号： G11C16/16 ,  G11C16/3409 ,  G11C16/345 ,  G11C16/3477

    摘要： An erase operation for a flash memory device includes identifying a sector group including a plurality of sectors based on an address, simultaneously pre-programming the sectors in the sector group, simultaneously erasing the sectors the sector group, and simultaneously post-programming the sectors in the sector group.

    摘要翻译： 闪存器件的擦除操作包括基于地址识别包括多个扇区的扇区组，同时对扇区组中的扇区进行预编程，同时擦除扇区组，并同时对扇区进行后编程 行业组。

    Flash memory device having column predecoder capable of selecting all column selection transistors and stress test method thereof
    8.
    发明授权
    Flash memory device having column predecoder capable of selecting all column selection transistors and stress test method thereof 有权
    具有能够选择所有列选择晶体管的列预解码器的闪存器件及其压力测试方法

    公开(公告)号：US07123528B2

    公开(公告)日：2006-10-17

    申请号：US10677841

    申请日：2003-10-01

    申请人： Jae-Yong Jeong ,  Heung-Soo Lim

    发明人： Jae-Yong Jeong ,  Heung-Soo Lim

    IPC分类号： G11C29/00

    CPC分类号： G11C29/34 ,  G11C8/12 ,  G11C16/04 ,  G11C2029/1204 ,  G11C2029/2602

    摘要： A column predecoder includes a buffer unit for inputting all column selection signals, decoder units for decoding an output of the buffer unit and column addresses, and level shifters for shifting voltage levels of column selection signals coupled to gates of the column selection transistors in response to an output of the decoder units. Since a ground voltage is applied to a bitline and a high voltage is applied to all column selection signals during the stress test, the stress test time can be shortened.

    摘要翻译： 列预解码器包括用于输入所有列选择信号的缓冲单元，用于对缓冲单元和列地址的输出进行解码的解码器单元和用于响应于列选择晶体管的栅极耦合到列选择晶体管的列选择信号的电压电平的电平移位器 解码器单元的输出。 由于接地电压施加于位线，并且在应力测试期间对所有列选择信号施加高电压，所以可以缩短应力测试时间。

    Non-volatile memory device and method of programming same
    9.
    发明申请
    Non-volatile memory device and method of programming same 失效
    非易失性存储器件和编程方法相同

    公开(公告)号：US20060087891A1

    公开(公告)日：2006-04-27

    申请号：US11257074

    申请日：2005-10-25

    申请人： Jae-Yong Jeong ,  Heung-Soo Lim

    发明人： Jae-Yong Jeong ,  Heung-Soo Lim

    IPC分类号： G11C16/04

    CPC分类号： G11C16/10 ,  G11C16/24

    摘要： Disclosed are a non-volatile memory device and a method of programming the same. The method comprises applying a wordline voltage, a bitline voltage, and a bulk voltage to a memory cell during a plurality of program loops. In cases where the bitline voltage falls below a first predetermined detection voltage during a current program loop, or the bulk voltage becomes higher than a second predetermined detection voltage, the same wordline voltage is used in the current programming loop and a next program loop following the current program loop. Otherwise, the wordline voltage is incremented by a predetermined amount before the next programming loop.

    摘要翻译： 公开了一种非易失性存储器件及其编程方法。 该方法包括在多个程序循环期间将字线电压，位线电压和体电压施加到存储器单元。 在当前程序循环期间位线电压下降到低于第一预定检测电压或体电压变得高于第二预定检测电压的情况下，在当前编程环路中使用相同的字线电压，并在下一个程序循环 当前程序循环。 否则，在下一个编程循环之前，字线电压增加预定量。