利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

5 条记录 (耗时 0.025 秒)

    MEMORY DEVICES AND PROGRAM METHODS THEREOF
    4.
    发明申请
    MEMORY DEVICES AND PROGRAM METHODS THEREOF 有权
    存储器件及其程序方法

    公开(公告)号：US20120300561A1

    公开(公告)日：2012-11-29

    申请号：US13476196

    申请日：2012-05-21

    申请人： Sung-Won YUN ,  ChiWeon YOON ,  Kyung-Hwa KANG ,  JinTae KIM

    发明人： Sung-Won YUN ,  ChiWeon YOON ,  Kyung-Hwa KANG ,  JinTae KIM

    IPC分类号： G11C5/14 ,  G11C7/00

    CPC分类号： G11C5/025 ,  G11C5/145 ,  G11C8/08 ,  G11C8/14 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/30

    摘要： Memory devices and program methods thereof, the memory devices including a memory cell array with a three-dimensional structure, a voltage generator configured to supply a pass voltage and a program voltage to the memory cell array, and a control logic configured to make the rising slope of the pass voltage variable with a program loop during a program operation. The memory device may improve a program speed by adjusting the rising slope of the pass voltage according to the program loop.

    摘要翻译： 存储器件及其编程方法，所述存储器件包括具有三维结构的存储单元阵列，被配置为向所述存储单元阵列提供通过电压和编程电压的电压发生器，以及配置为使所述上升的控制逻辑 程序运行期间程序循环的通过电压变量的斜率。 存储器件可以通过根据程序循环调整通过电压的上升沿来提高编程速度。

    NONVOLATILE MEMORY DEVICES, OPERATING METHODS THEREOF AND MEMORY SYSTEMS INCLUDING THE SAME
    5.
    发明申请
    NONVOLATILE MEMORY DEVICES, OPERATING METHODS THEREOF AND MEMORY SYSTEMS INCLUDING THE SAME 审中-公开
    非易失性存储器件，其操作方法和包括其的存储器系统

    公开(公告)号：US20150170749A1

    公开(公告)日：2015-06-18

    申请号：US14631341

    申请日：2015-02-25

    申请人： Sang-Won PARK ,  Dongku KANG ,  Jung-Yun YUN ,  Jinman HAN ,  ChiWeon YOON

    发明人： Sang-Won PARK ,  Dongku KANG ,  Jung-Yun YUN ,  Jinman HAN ,  ChiWeon YOON

    IPC分类号： G11C16/14 ,  G11C16/34 ,  G11C16/04

    CPC分类号： G11C16/14 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3445 ,  H01L27/11582

    摘要： The inventive concept relates to a nonvolatile memory device and methods for operating the same. The nonvolatile memory device comprises a plurality of strings arranged in rows and columns on a substrate, each string including at least one ground select transistor, a plurality of memory cells and at least one string select transistor sequentially stacked on the substrate. The method comprises erasing first memory cells corresponding to an erasure failed row and inhibiting erasure of second memory cells corresponding to an erasure passed row, and performing an erasure verification by a unit of each row with respect to the first memory cells.

    摘要翻译： 本发明构思涉及非易失性存储器件及其操作方法。 非易失性存储器件包括在衬底上以行和列布置的多个串，每个串包括至少一个接地选择晶体管，多个存储器单元和顺序堆叠在衬底上的至少一个串选择晶体管。 该方法包括：擦除对应于擦除失败行的第一存储单元，并禁止对与擦除通过的行相对应的第二存储单元的擦除，并以相对于第一存储单元的每行为单位进行擦除验证。