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    NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
    4.
    发明申请
    NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 有权
    非易失性存储器件和包括其的存储器系统

    公开(公告)号：US20130170297A1

    公开(公告)日：2013-07-04

    申请号：US13619118

    申请日：2012-09-14

    申请人： Sang-Wan NAM ,  Kyung-Hwa KANG ,  Junghoon PARK

    发明人： Sang-Wan NAM ,  Kyung-Hwa KANG ,  Junghoon PARK

    IPC分类号： G11C16/04

    CPC分类号： G11C16/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11582

    摘要： According to example embodiments, a nonvolatile memory device includes a first and a second NAND string. The first NAND string includes a first string selection transistor, a first local ground and a first global ground selection transistor, and first memory cells stacked in a direction perpendicular to a substrate. The second NAND string includes a second string selection transistor, a second local ground and a second global ground selection transistor, and second memory cells stacked in the direction perpendicular to the substrate. The device includes a selection line driver including path transistors configured to select and provide at least one operation voltage to the first and second string selection transistors, the first and second local and global ground selection transistors. The first and second string selection transistors are electrically isolated from each other, and the first and second global ground selection transistors are electrically connected.

    摘要翻译： 根据示例性实施例，非易失性存储器件包括第一和第二NAND串。 第一NAND串包括第一串选择晶体管，第一局部地和第一全局接地选择晶体管，以及沿垂直于衬底的方向堆叠的第一存储单元。 第二NAND串包括第二串选择晶体管，第二局部地和第二全局接地选择晶体管，以及沿与基板垂直的方向堆叠的第二存储单元。 该器件包括选择线驱动器，其包括被配置为选择并向第一和第二串选择晶体管，第一和第二局部和全局地选择晶体管提供至少一个操作电压的路径晶体管。 第一和第二串选择晶体管彼此电绝缘，并且第一和第二全局接地选择晶体管电连接。

    NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME
    6.
    发明申请
    NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME 审中-公开

    公开(公告)号：US20150221387A1

    公开(公告)日：2015-08-06

    申请号：US14681748

    申请日：2015-04-08

    申请人： Sang-Wan NAM

    发明人： Sang-Wan NAM

    IPC分类号： G11C16/34 ,  G11C16/26

    CPC分类号： G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3459 ,  H01L27/11582

    摘要： According to example embodiments, an operation method of a nonvolatile memory device includes determining a location of a selected word line among word lines connected to the nonvolatile memory device, selecting one of a plurality of different read disturbance reducing modes according to the location of the selected word line, and performing a read or verification operation according to the selected read disturbance reducing modes. The nonvolatile memory device includes cell strings. Each one of the cell strings includes memory cells stacked on top of each other in a direction perpendicular to the substrate and between a ground select transistor and a string select transistor. The ground select transistor is between the substrate and the number of the memory cells. The string select transistor is connected to a bit line and is between the bit line and the number of the memory cells.

    NONVOLATILE MEMORY DEVICE AND ERASING METHOD THEREOF
    8.
    发明申请
    NONVOLATILE MEMORY DEVICE AND ERASING METHOD THEREOF 有权
    非易失性存储器件及其擦除方法

    公开(公告)号：US20150325301A1

    公开(公告)日：2015-11-12

    申请号：US14574079

    申请日：2014-12-17

    申请人： Sang-Wan NAM

    发明人： Sang-Wan NAM

    IPC分类号： G11C16/14

    CPC分类号： G11C16/16 ,  G11C16/0483 ,  G11C16/14

    摘要： According to example embodiments, a nonvolatile memory device includes a lower filling insulating layer covering a peripheral logic structure on a substrate, a horizontal semiconductor layer on the lower filling insulating layer, and a three-dimensional memory cell array including a plurality of memory blocks on the horizontal semiconductor layer. The horizontal semiconductor layer includes a plurality of doped regions spaced apart from each other in a first direction and a plurality of well regions between the doped regions. Each of the memory blocks includes sub-blocks on corresponding ones of the well regions. The non-volatile memory device is configured to perform an erase operation in units of the sub-blocks. The non-volatile memory device is configured to independently apply an erase voltage to a selected one of the well regions during the erase operation.

    摘要翻译： 根据示例性实施例，非易失性存储器件包括覆盖衬底上的外围逻辑结构的下填充绝缘层，下填充绝缘层上的水平半导体层和包括多个存储块的三维存储单元阵列 水平半导体层。 水平半导体层包括在第一方向彼此间隔开的多个掺杂区域和在掺杂区域之间的多个阱区域。 每个存储块包括对应的井区域中的子块。 非易失性存储器件被配置为以子块为单位执行擦除操作。 非易失性存储器件被配置为在擦除操作期间将擦除电压独立地施加到所选择的一个阱区。

    NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME
    9.
    发明申请
    NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME 有权
    非易失性存储器件及其操作方法

    公开(公告)号：US20150221373A1

    公开(公告)日：2015-08-06

    申请号：US14608760

    申请日：2015-01-29

    申请人： Sang-Wan NAM

    发明人： Sang-Wan NAM

    IPC分类号： G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C16/08

    CPC分类号： G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3459 ,  H01L27/11582

    摘要： According to example embodiments, an operation method of a nonvolatile memory device includes determining a location of a selected word line among word lines connected to the nonvolatile memory device, selecting one of a plurality of different read disturbance reducing modes according to the location of the selected word line, and performing a read or verification operation according to the selected read disturbance reducing modes. The nonvolatile memory device includes cell strings. Each one of the cell strings includes memory cells stacked on top of each other in a direction perpendicular to the substrate and between a ground select transistor and a string select transistor. The ground select transistor is between the substrate and the number of the memory cells. The string select transistor is connected to a bit line and is between the bit line and the number of the memory cells.

    摘要翻译： 根据示例实施例，非易失性存储器件的操作方法包括：确定连接到非易失性存储器件的字线中所选字线的位置，根据所选择的位置选择多个不同的读干扰减少模式之一 字线，并且根据所选择的读取干扰降低模式执行读取或验证操作。 非易失性存储器件包括单元串。 单元串中的每一个包括在垂直于衬底的方向上以及接地选择晶体管和串选择晶体管之间彼此叠置的存储单元。 接地选择晶体管位于衬底和存储器单元的数量之间。 串选择晶体管连接到位线，位于位线和存储单元数之间。

    NONVOLATILE MEMORY DEVICE AND CONTROL METHOD THEREOF
    10.
    发明申请
    NONVOLATILE MEMORY DEVICE AND CONTROL METHOD THEREOF 有权
    非易失性存储器件及其控制方法

    公开(公告)号：US20140226397A1

    公开(公告)日：2014-08-14

    申请号：US14104406

    申请日：2013-12-12

    申请人： Yang-Lo AHN ,  Sang-Wan NAM ,  Sang-Won SHIM

    发明人： Yang-Lo AHN ,  Sang-Wan NAM ,  Sang-Won SHIM

    IPC分类号： G11C16/34

    CPC分类号： G11C16/3427 ,  G11C16/3422

    摘要： A vertical nonvolatile memory device which includes a plurality of cell strings formed in a direction intersecting with a substrate is provided. The vertical nonvolatile memory device is configured to apply a non-selection read voltage to at least one selection line connected to a cell string from among the plurality of cell strings. The vertical nonvolatile memory device is configured to apply the non-selection read voltage to at least one unselected word line of the cell string a desired time period after the applying of the non-selection read voltage to the at least one selection line.

    摘要翻译： 提供一种垂直非易失性存储装置，其包括在与基板相交的方向上形成的多个单元串。 垂直非易失性存储器件被配置为向多个单元串中的连接到单元串的至少一个选择线施加非选择读取电压。 垂直非易失性存储器件被配置为在将非选择读取电压施加到至少一个选择线之后的所需时间周期内将非选择读取电压施加到单元串的至少一个未选择的字线。