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    Control of cells, modules and a pack comprised of hybridized electrochemistries
    1.
    发明授权
    Control of cells, modules and a pack comprised of hybridized electrochemistries 有权
    控制细胞，模块和由杂化电化学组成的包装

    公开(公告)号：US08396609B2

    公开(公告)日：2013-03-12

    申请号：US12614192

    申请日：2009-11-06

    申请人： Chia Wei Wang ,  Ann Marie Sastry ,  Fabio Albano

    发明人： Chia Wei Wang ,  Ann Marie Sastry ,  Fabio Albano

    IPC分类号： G05D11/00

    CPC分类号： H02J7/0013 ,  H01M10/052 ,  H01M10/0562 ,  H01M10/42

    摘要： A power management apparatus for a hybridized energy device includes a hybridized energy device including a plurality of units. The units include electrical energy storage and/or gathering cells, in series or in parallel to form a module. A plurality of the modules in series or in parallel form a pack. The power management apparatus also includes a central management apparatus (CMA) interconnecting a plurality of module management apparatus (MMAs) by means of either wired or wireless connections and a plurality of MMAs. Each MMA interconnects with a plurality of unit management apparatuses by means of either wireless or wired communication circuits. The power management apparatus further includes a plurality of units management apparatuses (UMAs), each wired, connected with, or deposited on a unit. Furthermore, the power management apparatus includes a rechargeable battery power source for a CMA, a plurality of MMAs, and a plurality of UMAs.

    摘要翻译： 用于混合能量装置的电力管理装置包括包括多个单元的杂交能量装置。 这些单元包括串联或并联的电能存储和/或收集单元以形成模块。 串联或并联的多个模块形成一个包装。 电力管理装置还包括通过有线或无线连接和多个MMA互连多个模块管理装置（MMA）的中央管理装置（CMA）。 每个MMA通过无线或有线通信电路与多个单元管理装置互连。 电力管理装置还包括多个单元管理装置（UMA），每个单元管理装置连接，连接或放置在一个单元上。 此外，电力管理装置包括用于CMA的可再充电电池电源，多个MMA和多个UMA。

    CONTROL OF CELLS, MODULES AND A PACK COMPRISED OF HYBRIDIZED ELECTROCHEMISTRIES
    4.
    发明申请
    CONTROL OF CELLS, MODULES AND A PACK COMPRISED OF HYBRIDIZED ELECTROCHEMISTRIES 有权
    控制细胞，模块和包含杂化电化学的包装

    公开(公告)号：US20100138072A1

    公开(公告)日：2010-06-03

    申请号：US12614192

    申请日：2009-11-06

    申请人： Chia Wei Wang ,  Ann Marie Sastry ,  Fabio Albano

    发明人： Chia Wei Wang ,  Ann Marie Sastry ,  Fabio Albano

    IPC分类号： G06F1/28 ,  G06F1/26 ,  G06F17/10

    CPC分类号： H02J7/0013 ,  H01M10/052 ,  H01M10/0562 ,  H01M10/42

    摘要： A power management apparatus for a hybridized energy device includes a hybridized energy device including a plurality of units. The units include electrical energy storage and/or gathering cells, in series or in parallel to form a module. A plurality of the modules in series or in parallel form a pack. The power management apparatus also includes a central management apparatus (CMA) interconnecting a plurality of module management apparatus (MMAs) by means of either wired or wireless connections and a plurality of MMAs. Each MMA interconnects with a plurality of unit management apparatuses by means of either wireless or wired communication circuits. The power management apparatus further includes a plurality of units management apparatuses (UMAs), each wired, connected with, or deposited on a unit. Furthermore, the power management apparatus includes a rechargeable battery power source for a CMA, a plurality of MMAs, and a plurality of UMAs.

    摘要翻译： 用于混合能量装置的电力管理装置包括包括多个单元的杂交能量装置。 这些单元包括串联或并联的电能存储和/或收集单元以形成模块。 串联或并联的多个模块形成一个包装。 电力管理装置还包括通过有线或无线连接和多个MMA互连多个模块管理装置（MMA）的中央管理装置（CMA）。 每个MMA通过无线或有线通信电路与多个单元管理装置互连。 电力管理装置还包括多个单元管理装置（UMA），每个单元管理装置连接，连接或放置在一个单元上。 此外，电力管理装置包括用于CMA的可再充电电池电源，多个MMA和多个UMA。

    Circuit and method for an SRAM with two phase word line pulse
    7.
    发明申请
    Circuit and method for an SRAM with two phase word line pulse 有权
    具有两相字线脉冲的SRAM的电路和方法

    公开(公告)号：US20080106963A1

    公开(公告)日：2008-05-08

    申请号：US11811659

    申请日：2007-06-11

    申请人： Chia Wei Wang ,  Cheng Hung Lee ,  Hung-Jen Liao ,  Fu-Chieh Hsu

    发明人： Chia Wei Wang ,  Cheng Hung Lee ,  Hung-Jen Liao ,  Fu-Chieh Hsu

    IPC分类号： G11C7/02 ,  G11C8/00

    CPC分类号： G11C11/418 ,  G11C8/08

    摘要： A circuit and method for providing a two phase word line pulse for use during access cycles in an SRAM memory with improved operating margins. A first and a second timing circuit are provided and a word line voltage suppression circuit is provided to reduce the voltage on the active word lines in a first phase of a word line pulse, and to allow the word lines to rise to a second, unsuppressed voltage in a second phase of the word line pulse, responsive to the first and second timing circuits. The first and second timing circuits observe the bit lines voltage discharge and provide control signals active when the bit lines are discharged past certain thresholds, these signals control the voltage suppression circuit. Operating margins for the SRAM are therefore improved. Methods for operating an SRAM using a two phase word line pulse are provided.

    摘要翻译： 一种电路和方法，用于在具有改进的操作余量的SRAM存储器中的访问周期期间提供两相字线脉冲。 提供第一和第二定时电路，并且提供字线电压抑制电路以减小字线脉冲的第一相中有效字线上的电压，并允许字线上升到第二，未压缩 响应于第一和第二定时电路在字线脉冲的第二相位中的电压。 第一和第二定时电路观察位线电压放电，并且当位线经过某些阈值时提供控制信号有效，这些信号控制电压抑制电路。 因此，SRAM的工作裕度得到改善。 提供了使用两相字线脉冲来操作SRAM的方法。

    Memory circuit and tracking circuit thereof
    8.
    发明授权
    Memory circuit and tracking circuit thereof 有权
    存储电路及其跟踪电路

    公开(公告)号：US07889583B2

    公开(公告)日：2011-02-15

    申请号：US12841804

    申请日：2010-07-22

    申请人： Chia Wei Wang

    发明人： Chia Wei Wang

    IPC分类号： G11C29/00

    CPC分类号： G11C7/12 ,  G11C8/08

    摘要： A tracking circuit of a memory circuit is provided. The tracking circuit is coupled between a control circuit and a sense amplifier, delays a word-line pulse signal generated by the control circuit by a delay period to generate a sense amplifier enable signal enabling the sense amplifier to detect data bits output by a memory cell array. In one embodiment, the tracking circuit comprises a plurality of dummy cells and a dummy bit line. At least one of the plurality of dummy cells comprises a plurality of cascaded transistors cascaded between the dummy bit line and a ground voltage for lowering down a dummy bit line signal on the dummy bit line when the word-line pulse signal is enabled. The dummy bit line is coupled to the dummy cells and carries the dummy bit line signal.

    摘要翻译： 提供了存储器电路的跟踪电路。 跟踪电路耦合在控制电路和读出放大器之间，将由控制电路产生的字线脉冲信号延迟延迟周期以产生读出放大器使能信号，使得读出放大器能够检测由存储器单元输出的数据位 数组。 在一个实施例中，跟踪电路包括多个虚拟单元和虚拟位线。 多个虚拟单元中的至少一个包括级联在虚拟位线和地电压之间的多个级联的晶体管，用于当字线脉冲信号被使能时降低虚拟位线上的虚拟位线信号。 虚拟位线耦合到虚拟单元并且携带虚拟位线信号。

    MEMORY CIRCUIT AND TRACKING CIRCUIT THEREOF
    9.
    发明申请
    MEMORY CIRCUIT AND TRACKING CIRCUIT THEREOF 有权
    存储器电路和跟踪电路

    公开(公告)号：US20100118628A1

    公开(公告)日：2010-05-13

    申请号：US12266593

    申请日：2008-11-07

    申请人： Chia Wei Wang

    发明人： Chia Wei Wang

    IPC分类号： G11C7/00 ,  G11C8/08

    CPC分类号： G11C7/12 ,  G11C7/08 ,  G11C8/08

    摘要： The invention provides a tracking circuit of a memory circuit. The tracking circuit is coupled between a control circuit and a sense amplifier, delays a word-line pulse signal generated by the control circuit by a delay period to generate a sense amplifier enable signal enabling the sense amplifier to detect data bits output by a memory cell array. In one embodiment, the tracking circuit comprises a plurality of dummy cells, a dummy bit line, and an inverter. At least one of the plurality of dummy cells comprises a plurality of cascaded transistors cascaded between the dummy bit line and a ground voltage for pulling down the voltage of the dummy bit line when the word-line pulse signal is enabled. The dummy bit line is coupled between the dummy cells and the inverter. The inverter inverts the voltage of the dummy bit line to generate the sense amplifier enable signal.

    摘要翻译： 本发明提供一种存储器电路的跟踪电路。 跟踪电路耦合在控制电路和读出放大器之间，将由控制电路产生的字线脉冲信号延迟延迟周期以产生读出放大器使能信号，使得读出放大器能够检测由存储器单元输出的数据位 数组。 在一个实施例中，跟踪电路包括多个虚拟单元，虚拟位线和反相器。 所述多个虚拟单元中的至少一个包括在所述虚拟位线和级联在所述虚拟位线和地电压之间的多个级联的晶体管，用于当所述字线脉冲信号被使能时，用于下拉所述虚拟位线的电压。 虚拟位线耦合在虚拟单元和逆变器之间。 逆变器使虚拟位线的电压反相，产生读出放大器使能信号。

    Memory Circuit and Tracking Circuit Thereof
    10.
    发明申请
    Memory Circuit and Tracking Circuit Thereof 有权
    存储电路及其跟踪电路

    公开(公告)号：US20100284232A1

    公开(公告)日：2010-11-11

    申请号：US12841804

    申请日：2010-07-22

    申请人： Chia Wei Wang

    发明人： Chia Wei Wang

    IPC分类号： G11C7/00 ,  G11C7/06

    CPC分类号： G11C7/12 ,  G11C8/08

    摘要： The invention provides a tracking circuit of a memory circuit. The tracking circuit is coupled between a control circuit and a sense amplifier, delays a word-line pulse signal generated by the control circuit by a delay period to generate a sense amplifier enable signal enabling the sense amplifier to detect data bits output by a memory cell array. In one embodiment, the tracking circuit comprises a plurality of dummy cells and a dummy bit line. At least one of the plurality of dummy cells comprises a plurality of cascaded transistors cascaded between the dummy bit line and a ground voltage for lowering down a dummy bit line signal on the dummy bit line when the word-line pulse signal is enabled. The dummy bit line is coupled to the dummy cells and carries the dummy bit line signal.

    摘要翻译： 本发明提供一种存储器电路的跟踪电路。 跟踪电路耦合在控制电路和读出放大器之间，将由控制电路产生的字线脉冲信号延迟延迟周期以产生读出放大器使能信号，使得读出放大器能够检测由存储器单元输出的数据位 数组。 在一个实施例中，跟踪电路包括多个虚拟单元和虚拟位线。 所述多个虚拟单元中的至少一个包括在所述虚拟位线和地电压之间级联的多个级联晶体管，用于当所述字线脉冲信号被使能时降低所述虚拟位线上的虚拟位线信号。 虚拟位线耦合到虚拟单元并且携带虚拟位线信号。