公开(公告)号：US06248643B1

公开(公告)日：2001-06-19

申请号：US09285534

申请日：1999-04-02

申请人： Chien-Sheng Hsieh ,  Wei-Ray Lin ,  Fu-Liang Yang ,  Erik S. Jeng ,  Bor-Ru Sheu

发明人： Chien-Sheng Hsieh ,  Wei-Ray Lin ,  Fu-Liang Yang ,  Erik S. Jeng ,  Bor-Ru Sheu

IPC分类号： H01L2176

CPC分类号： H01L21/76897 ,  H01L21/32053 ,  H01L21/76224 ,  H01L21/76879 ,  H01L21/76885

摘要： A method for fabricating self-aligned contacts using elevated trench isolation, selective contact plug deposition and planarization starting at the device level. The process begins by successively forming a gate oxide layer and a first gate electrode layer on a silicon substrate. Next, fully planarized trench isolation regions are formed using sacrificial oxide and nitride layers and selective etching. A sacrificial pad oxide layer and a first sacrificial nitride layer are formed. The first sacrificial nitride layer, the sacrificial pad oxide layer, the first gate electrode layer, the gate oxide layer, and the silicon substrate are patterned to form trenches. A fill oxide layer is deposited in the trenches and over the first sacrificial nitride layer. An oxide etch is performed which recesses the fill oxide layer in the trenches below the level of the top of the first nitride layer. A second sacrificial nitride layer is formed on the fill oxide layer and over the first sacrificial nitride layer. Chemical-mechanical polishing is performed. Successive oxide etch, nitride etch and oxide etch steps are performed defining elevated trench isolation regions fully planarized with the first gate electrode layer. A silicide layer, a dielectric layer and a top nitride layer are formed. The top nitride layer, the dielectric layer, the silicide layer, the first gate electrode layer and the gate oxide layer are patterned forming gate structures between elevated trench isolation regions and conductive lines on elevated trench isolation regions. Spacers are formed on the sidewalls of the gate structures, the conductive lines and the elevated trench isolation regions. Then, self-aligned contact plugs are formed adjacent to the spacers.

摘要翻译： 一种使用升高的沟槽隔离，选择性接触插塞沉积和平面化从器件级开始制造自对准触点的方法。 该工艺开始于在硅衬底上依次形成栅氧化层和第一栅电极层。 接下来，使用牺牲氧化物和氮化物层和选择性蚀刻形成完全平坦化的沟槽隔离区域。 形成牺牲衬垫氧化物层和第一牺牲氮化物层。 图案化第一牺牲氮化物层，牺牲焊盘氧化物层，第一栅极电极层，栅极氧化物层和硅衬底以形成沟槽。 填充氧化物层沉积在沟槽中并在第一牺牲氮化物层上方。 执行氧化物蚀刻，其将沟槽中的填充氧化物层的凹陷低于第一氮化物层的顶部的水平面。 第二牺牲氮化物层形成在填充氧化物层上并在第一牺牲氮化物层上方。 进行化学机械抛光。 执行连续氧化物蚀刻，氮化物蚀刻和氧化物蚀刻步骤，定义与第一栅极电极层完全平坦化的升高的沟槽隔离区域。 形成硅化物层，电介质层和顶部氮化物层。 在顶部氮化物层，电介质层，硅化物层，第一栅极电极层和栅极氧化物层之间，在升高的沟槽隔离区域和升高的沟槽隔离区域上的导电线之间构图形成栅极结构。 隔板形成在栅极结构，导电线和升高的沟槽隔离区的侧壁上。 然后，在间隔物附近形成自对准的接触塞。

公开(公告)号：US06180489B2

公开(公告)日：2001-01-30

申请号：US09290922

申请日：1999-04-12

申请人： Fu-Liang Yang ,  Bih-Tiao Lin ,  Wei-Ray Lin ,  Erik S. Jeng

发明人： Fu-Liang Yang ,  Bih-Tiao Lin ,  Wei-Ray Lin ,  Erik S. Jeng

IPC分类号： H01L2176

CPC分类号： H01L21/76229

摘要： A method for forming planarized shallow trench isolation is described. A nitride layer is deposited over the surface of a semiconductor substrate. A plurality of isolation trenches are etched through the nitride layer into the semiconductor substrate wherein there are at least one wide trench and at least one narrow trench. A first oxide layer is deposited over the first nitride layer and within the isolation trenches wherein the first oxide layer fills the isolation trenches. A capping nitride layer is deposited overlying the first oxide layer. A second oxide layer is deposited overlying the capping nitride layer. The second oxide layer is polished away wherein the second oxide layer and the capping nitride layer are left only within the wide trench. The first and second oxide layers are dry etched away with an etch stop on the capping nitride layer within the wide trench and the first nitride layer wherein the second oxide layer is completely removed. Thereafter, the first oxide layer is overetched to leave the top surface of the first oxide layer just above the bottom surface of the first nitride layer and the capping nitride layer within the wide trench. The capping nitride layer and the first nitride layer are removed completing the formation of shallow trench isolation regions in the fabrication of an integrated circuit device.

摘要翻译： 描述了形成平坦化浅沟槽隔离的方法。 在半导体衬底的表面上沉积氮化物层。 通过氮化物层将多个隔离沟槽蚀刻到半导体衬底中，其中存在至少一个宽沟槽和至少一个窄沟槽。 第一氧化物层沉积在第一氮化物层之上并且在隔离沟槽内，其中第一氧化物层填充隔离沟槽。 覆盖第一氧化物层的覆盖氮化物层被沉积。 覆盖覆盖氮化物层的第二氧化物层被沉积。 抛光第二氧化物层，其中第二氧化物层和覆盖氮化物层仅留在宽沟槽内。 第一氧化物层和第二氧化物层在宽沟槽内的覆盖氮化物层上的蚀刻停止层和第二氧化物层被完全去除的第一氮化物层被干蚀刻掉。 此后，将第一氧化物层过蚀刻，以将第一氧化物层的顶表面刚好在第一氮化物层的底表面和宽沟槽内的覆盖氮化物层的上方。 在制造集成电路器件时，去除覆盖氮化物层和第一氮化物层，从而形成浅沟槽隔离区。

公开(公告)号：US6060348A

公开(公告)日：2000-05-09

申请号：US184341

申请日：1998-11-02

申请人： Fu-Liang Yang ,  Wei-Ray Lin ,  Ming-Hong Kuo ,  Erik S. Jeng

发明人： Fu-Liang Yang ,  Wei-Ray Lin ,  Ming-Hong Kuo ,  Erik S. Jeng

IPC分类号： H01L21/762 ,  H01L21/8238 ,  H01L21/76

CPC分类号： H01L21/76202 ,  H01L21/76224

摘要： A method for forming planarized isolation by combining LOCOS and STI isolation processes is described. A first nitride layer is deposited over a pad oxide layer on the surface of a semiconductor substrate. The first nitride layer and pad oxide layer are etched through where they are not covered by a mask to provide openings where the surface of the semiconductor substrate is exposed wherein there is at least one wide opening and one narrow opening. A second nitride layer is deposited over the substrate and etched back to leave spacers on the sidewalls of the openings wherein the narrow opening is filled by the spacers. The exposed semiconductor substrate within the wide opening is oxidized wherein a field oxide region is formed within the wide opening. A portion of the first nitride layer and spacers is etched away whereby the semiconductor substrate within the narrow opening is exposed. A trench is etched into the semiconductor substrate where it is exposed within the narrow opening. An oxide layer is deposited overlying the first nitride layer and field oxide region and filling the trench wherein the oxide layer filling the trench forms a shallow trench isolation region. The oxide layer is polished away with a polish stop at the first nitride layer. The first nitride layer, the spacers, and the pad oxide layer are removed, completing formation of both a field oxide region and a shallow trench isolation region in the fabrication of an integrated circuit device.

摘要翻译： 描述了通过组合LOCOS和STI隔离过程形成平坦化隔离的方法。 在半导体衬底的表面上的衬垫氧化物层上沉积第一氮化物层。 蚀刻第一氮化物层和焊盘氧化物层，其中它们未被掩模覆盖，以提供其中存在至少一个宽开口和一个窄开口的半导体衬底的表面的开口。 第二氮化物层沉积在衬底上并被回蚀刻以在开口的侧壁上留下间隔物，其中窄的开口被间隔物填充。 在宽开口内的暴露的半导体衬底被氧化，其中在宽开口内形成场氧化物区域。 第一氮化物层和间隔物的一部分被蚀刻掉，由此暴露窄开口内的半导体衬底。 沟槽被蚀刻到半导体衬底中，其中它暴露在窄的开口内。 沉积覆盖在第一氮化物层和场氧化物区域上并填充沟槽的氧化物层，其中填充沟槽的氧化物层形成浅沟槽隔离区域。 在第一氮化物层处用抛光停止层抛光氧化物层。 去除第一氮化物层，间隔物和衬垫氧化物层，在集成电路器件的制造中完成场氧化物区域和浅沟槽隔离区域的形成。

公开(公告)号：US6140240A

公开(公告)日：2000-10-31

申请号：US226275

申请日：1999-01-07

申请人： Fu-Liang Yang ,  Bih-Tiao Lin ,  Tzu-Shih Yen ,  Bi-Ling Chen ,  Erik S. Jeng

发明人： Fu-Liang Yang ,  Bih-Tiao Lin ,  Tzu-Shih Yen ,  Bi-Ling Chen ,  Erik S. Jeng

IPC分类号： H01L21/3105 ,  H01L21/311 ,  H01L21/302

CPC分类号： H01L21/31053 ,  H01L21/31138

摘要： A method of removing microscratches in planarized dielectric surfaces covering conductor layers in submicron integrated circuit structures includes a semiconductor substrate having at least one dielectric layer formed thereon followed by a chemical mechanical polishing process for planarization. The removal of microscratches includes depositing a PE-CVD polymer layer to fill the microscratches, caused by CMP planarization, and to cover the planarized dielectric surface with a thin layer of the polymer. Deposition is followed by introducing an etching gas into the CVD chamber for an etch back of the just deposited polymer to well below the depth of the microscratches wherein the deposited polymer has the same etch rate as the dielectric layer formed thereunder.

摘要翻译： 在亚微米集成电路结构中的覆盖导体层的平坦化电介质表面中去除微结构的方法包括具有形成在其上的至少一个介电层，然后进行平面化的化学机械抛光工艺的半导体衬底。 去除微观尺度包括沉积PE-CVD聚合物层以填充由CMP平坦化引起的微观尺度，并用聚合物薄层覆盖平坦化的电介质表面。 沉积之后，将CVD蚀刻气体引入CVD室，以便正好沉积的聚合物的蚀刻深度远低于微细凹槽的深度，其中沉积的聚合物具有与其下形成的介电层相同的蚀刻速率。

公开(公告)号：US06278189B1

公开(公告)日：2001-08-21

申请号：US09428571

申请日：1999-10-28

申请人： Erik S. Jeng ,  Fu-Liang Yang ,  Tzu-Shih Yen

发明人： Erik S. Jeng ,  Fu-Liang Yang ,  Tzu-Shih Yen

IPC分类号： H01L2348

CPC分类号： H01L21/76897 ,  H01L21/76801 ,  H01L21/76804 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating contact holes in high density integrated circuits and the resulting structure are disclosed. It is shown that by judiciously integrating the process of forming shallow tapered holes with self-alignment techniques, self-aligned holes can be fabricated with reduced number of masking process steps. This is accomplished by first forming shallow tapered holes to a certain depth over certain regions in a substrate by means of isotropic etching and then extending them by anisotropic etching to full depth corresponding to the regions they are allowed to contact. The net result is a whole set of holes which are self-aligned and which are formed by means of a single photoresist mask.

摘要翻译： 公开了一种在高密度集成电路中制造接触孔的方法及其结构。 显示出通过明智地整合形成浅锥形孔的过程与自对准技术，可以以减少数量的掩模处理步骤来制造自对准的孔。 这是通过首先通过各向同性蚀刻在衬底中的某些区域上形成一定深度的浅锥形孔，然后通过各向异性蚀刻将它们扩展到对应于它们允许接触的区域的全深度来实现的。 最终的结果是整套孔是自对准的并且通过单个光致抗蚀剂掩模形成。

公开(公告)号：US5994228A

公开(公告)日：1999-11-30

申请号：US827818

申请日：1997-04-11

申请人： Erik S. Jeng ,  Fu-Liang Yang ,  Tzu-Shih Yen

发明人： Erik S. Jeng ,  Fu-Liang Yang ,  Tzu-Shih Yen

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L21/00 ,  H01L21/70

CPC分类号： H01L21/76897 ,  H01L21/76801 ,  H01L21/76804 ,  H01L23/485 ,  H01L2924/0002

摘要： A method for fabricating contact holes in high density integrated circuits and the resulting structure are disclosed. It is shown that by judiciously integrating the process of forming shallow tapered holes with self-alignment techniques, self-aligned holes can be fabricated with reduced number of masking process steps. This is accomplished by first forming shallow tapered holes to a certain depth over certain regions in a substrate by means of isotropic etching and then extending them by anisotropic etching to full depth corresponding to the regions they are allowed to contact. The net result is a whole set of holes which are self-aligned and which are formed by means of a single photoresist mask.

摘要翻译： 公开了一种在高密度集成电路中制造接触孔的方法及其结构。 显示出通过明智地整合形成浅锥形孔的过程与自对准技术，可以以减少数量的掩模处理步骤来制造自对准的孔。 这是通过首先通过各向同性蚀刻在衬底中的某些区域上形成一定深度的浅锥形孔，然后通过各向异性蚀刻将它们扩展到对应于它们允许接触的区域的全深度来实现的。 最终的结果是整套孔是自对准的并且通过单个光致抗蚀剂掩模形成。

公开(公告)号：US5834359A

公开(公告)日：1998-11-10

申请号：US924710

申请日：1997-08-29

申请人： Erik S. Jeng ,  Fu-Liang Yang

发明人： Erik S. Jeng ,  Fu-Liang Yang

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76202 ,  H01L21/76229 ,  H01L21/76235 ,  Y10S148/05

摘要： A method for forming an isolation region in a semiconductor substrate is disclosed. The present invention includes forming an insulating layer on the semiconductor substrate, and then forming a dielectric layer on the insulating layer. After patterning to etch portions of the dielectric layer, the insulating layer and the semiconductor substrate are etched using the patterned dielectric layer as a mask, thereby forming a trench in the semiconductor substrate. Next, a first silicon oxide layer is formed over the semiconductor substrate, and the first silicon oxide layer is then anisotropically etched to form a spacer on the sidewalls of the trench. Thereafter, the semiconductor substrate is thermally oxidized to form a field oxide region over the semiconductor substrate, and a second silicon oxide layer is then formed over the field oxide region. Finally, the second silicon oxide layer is etched back until surface of the dielectric layer is exposed.

摘要翻译： 公开了一种在半导体衬底中形成隔离区域的方法。 本发明包括在半导体衬底上形成绝缘层，然后在绝缘层上形成电介质层。 在图案化以蚀刻介电层的部分之后，使用图案化的电介质层作为掩模来蚀刻绝缘层和半导体衬底，从而在半导体衬底中形成沟槽。 接下来，在半导体衬底上形成第一氧化硅层，然后对第一氧化硅层进行各向异性蚀刻，以在沟槽的侧壁上形成间隔物。 此后，半导体衬底被热氧化以在半导体衬底上形成场氧化物区域，然后在场氧化物区域上形成第二氧化硅层。 最后，第二氧化硅层被回蚀，直到电介质层的表面露出。

公开(公告)号：US6071789A

公开(公告)日：2000-06-06

申请号：US190054

申请日：1998-11-10

申请人： Fu-Liang Yang ,  Erik S. Jeng ,  Bih-Tiao Lin ,  I-Ping Lee

发明人： Fu-Liang Yang ,  Erik S. Jeng ,  Bih-Tiao Lin ,  I-Ping Lee

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20

CPC分类号： H01L27/10894 ,  H01L28/60 ,  H01L21/76838 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10873 ,  H01L27/10897 ,  H01L28/55

摘要： A method for simultaneously forming a storage node and a plurality of interconnection in fabricating a semiconductor device on a substrate. The method comprises the steps of: forming a first dielectric layer over said cell array area and said periphery; forming a plurality of first contact holes through said first dielectric layer in said cell array area and said periphery area, said periphery area including a bitline and a word line, said word line and said bitline being used for addressing said memory cell; forming a first conductive layer in said plurality of first contact holes and on said first dielectric layer; patterning and etching said first conductive layer to form said storage node and said plurality of interconnections simultaneously; forming a second dielectric layer and a second conductive layer subsequently on said first dielectric layer, said storage node and said plurality of interconnections; and patterning and etching said second dielectric layer and said second conductive layer to form a charge storage means and a plurality of contact plugs.

摘要翻译： 一种用于在衬底上制造半导体器件的同时形成存储节点和多个互连的方法。 该方法包括以下步骤：在所述单元阵列区域和所述周边上形成第一介电层; 通过所述单元阵列区域和所述外围区域中的所述第一介电层形成多个第一接触孔，所述外围区域包括位线和字线，所述字线和所述位线用于寻址所述存储单元; 在所述多个第一接触孔和所述第一介电层上形成第一导电层; 图案化和蚀刻所述第一导电层以同时形成所述存储节点和所述多个互连; 随后在所述第一介电层，所述存储节点和所述多个互连上形成第二电介质层和第二导电层; 以及图案化和蚀刻所述第二介电层和所述第二导电层以形成电荷存储装置和多个接触插塞。

公开(公告)号：US5956594A

公开(公告)日：1999-09-21

申请号：US184345

申请日：1998-11-02

申请人： Fu-Liang Yang ,  Bi-Ling Chen ,  Erik S. Jeng

发明人： Fu-Liang Yang ,  Bi-Ling Chen ,  Erik S. Jeng

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/20

CPC分类号： H01L27/10894 ,  H01L21/76895 ,  H01L28/60 ,  H01L27/10852 ,  H01L27/10888

摘要： A method for creating a DRAM device, featuring the simultaneous formation of a capacitor plate, used for a stacked capacitor structure, and the formation of a metal contact structure, and of a word line contact structure, has been developed. The process features the deposition of a barrier layer, and an overlying tungsten layer, on a storage node electrode, and with the deposition also completely filling a metal contact hole, and a word line hole. A patterning procedure, using an anisotropic RIE procedure, removes unwanted regions of tungsten and barrier layer, resulting in a capacitor plate, a metal contact structure, and a word line structure, all comprised of tungsten and the barrier layers, and all formed via one deposition procedure, and patterned using one RIE procedure.

摘要翻译： 已经开发了用于产生用于层叠电容器结构的电容器板的同时形成以及金属接触结构的形成以及字线接触结构的DRAM器件的制造方法。 该方法的特征在于在存储节点电极上沉积阻挡层和覆盖的钨层，并且沉积也完全填充金属接触孔和字线孔。 使用各向异性RIE程序的图案化步骤去除钨和阻挡层的不需要的区域，导致电容器板，金属接触结构和字线结构，全部由钨和阻挡层组成，并且都通过一个 沉积程序，并使用一个RIE程序进行图案化。

公开(公告)号：US5804852A

公开(公告)日：1998-09-08

申请号：US876914

申请日：1997-06-16

申请人： Fu-Liang Yang ,  Erik S. Jeng

发明人： Fu-Liang Yang ,  Erik S. Jeng

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A multiple crown shaped polysilicon structure, used for a lower electrode of a DRAM stacked capacitor structure, has been developed. The multiple crown shaped, lower electrode, is formed overlying, and contacting a polysilicon fill layer, that is located between insulator encapsulated polycide gate structures. The polysilicon fill layer, in turn, contacts an underlying source/drain region of a transfer gate transistor. The multiple crown shaped lower electrode is comprised vertical polysilicon shapes, connected to an underlying, horizontal polysilicon shape, with the horizontal polysilicon shape overlying the polysilicon fill layer. One to three, vertical polysilicon shapes, are used on each side of the multiple crown shaped lower electrode.

摘要翻译： 已经开发了用于DRAM堆叠电容器结构的下电极的多冠状多晶硅结构。 形成多个冠状的下电极，其位于绝缘体封装的多晶硅栅极结构之间，覆盖并接触多晶硅填充层。 多晶硅填充层又接触传输栅晶体管的底层源/漏区。 多冠状下电极包括垂直多晶硅形状，连接到下面的水平多晶硅形状，其中水平多晶硅形状覆盖多晶硅填充层。 在多冠状下电极的每一侧使用一至三个垂直多晶硅形状。