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12 条记录 (耗时 0.036 秒)

    Feature dimension measurement
    1.
    发明授权
    Feature dimension measurement 有权
    特征尺寸测量

    公开(公告)号：US08049213B2

    公开(公告)日：2011-11-01

    申请号：US11958942

    申请日：2007-12-18

    申请人： Ching-Chung Su ,  Yi-Wei Chiu ,  Tzu Chan Weng ,  Yih Song Chiu ,  Pin Chia Su ,  Chih-Cherng Jeng ,  Kuo-Hsiu Wei

    发明人： Ching-Chung Su ,  Yi-Wei Chiu ,  Tzu Chan Weng ,  Yih Song Chiu ,  Pin Chia Su ,  Chih-Cherng Jeng ,  Kuo-Hsiu Wei

    IPC分类号： H01L21/66 ,  H01L23/544

    CPC分类号： H01L22/14 ,  H01L22/12 ,  H01L22/20

    摘要： A method of measuring dimensional characteristics includes providing a substrate and forming a reflective layer over the substrate. A dielectric layer is then formed over the reflective layer. The dielectric layer includes a grating pattern and a resistivity test line inset in a transparent region. Radiation is then directed onto the dielectric layer so that some of the radiation is transmitted through the transparent region to the reflective layer. A radiation pattern is then detected from the radiation reflected and scattered by the metal grating pattern. The radiation pattern is analyzed to determine a first dimensional information. Then the resistance of the resistivity test line is measured, and that resistance is analyzed to determine a second dimensional information. The first and second dimensional informations are then compared.

    摘要翻译： 测量尺寸特性的方法包括提供衬底并在衬底上形成反射层。 然后在反射层上形成电介质层。 电介质层包括在透明区域内插入的光栅图案和电阻率测试线。 然后将辐射引导到电介质层上，使得一些辐射透过透明区域到达反射层。 然后从由金属光栅图案反射和散射的辐射中检测出辐射图。 分析辐射图以确定第一维信息。 然后测量电阻率测试线的电阻，并分析该电阻以确定第二维信息。 然后比较第一和第二维信息。

    Feature Dimension Measurement
    2.
    发明申请
    Feature Dimension Measurement 有权
    特征尺寸测量

    公开(公告)号：US20090152545A1

    公开(公告)日：2009-06-18

    申请号：US11958942

    申请日：2007-12-18

    申请人： Ching-Chung Su ,  Yi-Wei Chiu ,  Tzu-Chan Weng ,  Yih Song Chiu ,  Pin Chia Su ,  Chih-Cherng Jeng ,  Kuo-Hsiu Wei

    发明人： Ching-Chung Su ,  Yi-Wei Chiu ,  Tzu-Chan Weng ,  Yih Song Chiu ,  Pin Chia Su ,  Chih-Cherng Jeng ,  Kuo-Hsiu Wei

    IPC分类号： H01L23/58 ,  H01L21/66

    CPC分类号： H01L22/14 ,  H01L22/12 ,  H01L22/20

    摘要： A method of measuring dimensional characteristics includes providing a substrate and forming a reflective layer over the substrate. A dielectric layer is then formed over the reflective layer. The dielectric layer includes a grating pattern and a resistivity test line inset in a transparent region. Radiation is then directed onto the dielectric layer so that some of the radiation is transmitted through the transparent region to the reflective layer. A radiation pattern is then detected from the radiation reflected and scattered by the metal grating pattern. The radiation pattern is analyzed to determine a first dimensional information. Then the resistance of the resistivity test line is measured, and that resistance is analyzed to determine a second dimensional information. The first and second dimensional informations are then compared.

    摘要翻译： 测量尺寸特性的方法包括提供衬底并在衬底上形成反射层。 然后在反射层上形成电介质层。 电介质层包括在透明区域内插入的光栅图案和电阻率测试线。 然后将辐射引导到电介质层上，使得一些辐射透过透明区域到达反射层。 然后从由金属光栅图案反射和散射的辐射中检测出辐射图。 分析辐射图以确定第一维信息。 然后测量电阻率测试线的电阻，并分析该电阻以确定第二维信息。 然后比较第一和第二维信息。

    Apparatus for wafer grinding
    4.
    发明授权
    Apparatus for wafer grinding 有权
    晶圆研磨设备

    公开(公告)号：US09120194B2

    公开(公告)日：2015-09-01

    申请号：US13188028

    申请日：2011-07-21

    申请人： Kuo-Hsiu Wei ,  Kei-Wei Chen ,  Ying-Lang Wang ,  Chun-Ting Kuo

    发明人： Kuo-Hsiu Wei ,  Kei-Wei Chen ,  Ying-Lang Wang ,  Chun-Ting Kuo

    IPC分类号： B24B7/22 ,  B24D7/14

    CPC分类号： B24B7/228 ,  B24D7/14

    摘要： A grinding wheel comprises an outer base with a first attached grain pad; and an inner frame with a second attached grain pad; and a spindle axis shared by the outer base and the inner frame, wherein at least one of the outer base and the inner frame can move independently along the shared spindle axis; and wherein the outer base, the inner frame, and the shared spindle axis all have a same center. A grinding system comprises an above said grinding wheel, and a wheel head attached to the shared spindle axis, capable of moving vertically, in addition to a motor driving the grinding wheel to spin; and a chuck table for fixing a wafer on top of the chuck table; wherein the grinding wheel overlaps a portion of the chuck table, each capable of spinning to the opposite direction of another.

    摘要翻译： 砂轮包括具有第一附接谷物垫的外基部; 以及具有第二附着谷物垫的内框架; 以及由所述外基座和所述内框架共享的主轴，其中所述外基座和所述内框架中的至少一个可以沿着所述共享主轴轴线独立地移动; 并且其中所述外基座，所述内框架和所述共享主轴轴线都具有相同的中心。 研磨系统包括上述砂轮和附接到共享主轴轴线的能够垂直移动的砂轮头，除了驱动砂轮旋转的马达之外， 以及用于将晶片固定在卡盘台顶部的卡盘台; 其中所述砂轮与所述卡盘台的一部分重叠，所述卡盘台的每一个能够沿相反方向旋转。

    Methods for minimizing edge peeling in the manufacturing of BSI chips
    5.
    发明授权
    Methods for minimizing edge peeling in the manufacturing of BSI chips 有权
    BSI芯片制造中边缘剥离最小化的方法

    公开(公告)号：US09064770B2

    公开(公告)日：2015-06-23

    申请号：US13551457

    申请日：2012-07-17

    申请人： Chun-Ting Kuo ,  Kei-Wei Chen ,  Ying-Lang Wang ,  Kuo-Hsiu Wei

    发明人： Chun-Ting Kuo ,  Kei-Wei Chen ,  Ying-Lang Wang ,  Kuo-Hsiu Wei

    IPC分类号： H01L21/02 ,  H01L27/146

    CPC分类号： H01L27/1464 ,  H01L21/02087 ,  H01L21/0209 ,  H01L27/14687

    摘要： A method includes forming top metal lines over a semiconductor substrate, wherein the semiconductor substrate is a portion of a wafer having a bevel. When the top metal lines are exposed, an etchant is supplied on the bevel, wherein regions of the wafer sprayed with the etchant has an inner defining line forming a first ring having a first diameter. A trimming step is performed to trim an edge portion of the wafer, wherein an edge of a remaining portion of the wafer has a second diameter substantially equal to or smaller than the first diameter.

    摘要翻译： 一种方法包括在半导体衬底上形成顶部金属线，其中半导体衬底是具有斜面的晶片的一部分。 当顶部金属线暴露时，在斜面上提供蚀刻剂，其中用蚀刻剂喷射的晶片的区域具有形成具有第一直径的第一环的内部限定线。 进行修整步骤以修剪晶片的边缘部分，其中晶片的剩余部分的边缘具有基本上等于或小于第一直径的第二直径。

    Modular grinding apparatuses and methods for wafer thinning
    7.
    发明授权
    Modular grinding apparatuses and methods for wafer thinning 有权
    用于晶片薄化的模块化研磨装置和方法

    公开(公告)号：US09570311B2

    公开(公告)日：2017-02-14

    申请号：US13370946

    申请日：2012-02-10

    申请人： Chun-Ting Kuo ,  Kei-Wei Chen ,  Ying-Lang Wang ,  Kuo-Hsiu Wei

    发明人： Chun-Ting Kuo ,  Kei-Wei Chen ,  Ying-Lang Wang ,  Kuo-Hsiu Wei

    IPC分类号： H01L21/304 ,  B24B37/04 ,  B24B37/00

    CPC分类号： H01L21/304 ,  B24B37/00 ,  B24B37/042

    摘要： Methods of thinning a plurality of semiconductor wafers and apparatuses for carrying out the same are disclosed. A grinding module within a set of grinding modules receives and grinds a semiconductor wafer. A polishing module receives the semiconductor wafer from the grinding module and polishes the wafer. The polishing module is configured to polish the semiconductor wafer in less time than the grinding module is configured to grind the corresponding wafer.

    摘要翻译： 公开了使多个半导体晶片变薄的方法及其实施方法。 一组研磨模块内的研磨模块接收并研磨半导体晶片。 抛光模块从研磨模块接收半导体晶片并抛光晶片。 抛光模块被配置为在比研磨模块构造成磨碎相应晶片的时间少的时间内抛光半导体晶片。

    Image Sensor Manufacturing Methods
    8.
    发明申请
    Image Sensor Manufacturing Methods 有权
    图像传感器制造方法

    公开(公告)号：US20130273686A1

    公开(公告)日：2013-10-17

    申请号：US13445766

    申请日：2012-04-12

    申请人： Mu-Han Cheng ,  Kuo-Hsiu Wei ,  Kei-Wei Chen ,  Ying-Lang Wang

    发明人： Mu-Han Cheng ,  Kuo-Hsiu Wei ,  Kei-Wei Chen ,  Ying-Lang Wang

    IPC分类号： H01L31/0232 ,  H01L21/28

    CPC分类号： H01L27/14623 ,  H01L27/1464 ,  H01L27/14687

    摘要： Semiconductor devices and back side illumination (BSI) sensor manufacturing methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a workpiece and forming an integrated circuit on a front side of the workpiece. A grid of a conductive material is formed on a back side of the workpiece using a damascene process.

    摘要翻译： 公开了半导体器件和背面照明（BSI）传感器制造方法。 在一个实施例中，制造半导体器件的方法包括提供工件并在工件的前侧形成集成电路。 使用镶嵌工艺在工件的背面上形成导电材料的格栅。

    Method and system for slurry usage reduction in chemical mechanical polishing
    9.
    发明授权
    Method and system for slurry usage reduction in chemical mechanical polishing 失效
    化学机械抛光中浆料用量减少的方法和系统

    公开(公告)号：US06769959B2

    公开(公告)日：2004-08-03

    申请号：US10050314

    申请日：2002-01-15

    申请人： Kei-Wei Chen ,  Ting-Chun Wang ,  Shih-Tzung Chang ,  Yu-Ku Lin ,  Ying-Lang Wang ,  Ming-Wen Chen ,  Kuo-Hsiu Wei

    发明人： Kei-Wei Chen ,  Ting-Chun Wang ,  Shih-Tzung Chang ,  Yu-Ku Lin ,  Ying-Lang Wang ,  Ming-Wen Chen ,  Kuo-Hsiu Wei

    IPC分类号： B24B100

    CPC分类号： B24B37/04 ,  B24B57/02

    摘要： A method and system is disclosed for reducing slurry usage in a chemical mechanical polishing operation utilizing at least one polishing pad thereof. Slurry can be intermittently supplied to a chemical mechanical polishing device. The slurry is generally flushed so that a portion of said slurry is trapped in a plurality of pores of at least one polishing pad associated with said chemical mechanical polishing device, wherein only a minimum amount of said slurry necessary is utilized to perform said chemical mechanical polishing operation, thereby reducing slurry usage and maintaining a consistent level of slurry removal rate performance and a decrease in particle defects thereof. The present invention thus discloses a method and system for intermittently delivering slurry to a chemical mechanical polishing device in a manner that significantly conserves slurry usage.

    摘要翻译： 公开了一种利用其至少一个抛光垫在化学机械抛光操作中减少浆料使用的方法和系统。 浆料可以间歇地供应到化学机械抛光装置。 通常将浆料冲洗，使得所述浆料的一部分被捕获在与所述化学机械抛光装置相关联的至少一个抛光垫的多个孔中，其中仅使用最少量的所需浆料来进行所述化学机械抛光 操作，从而减少浆料的使用并保持一致的浆料去除速率性能水平和其颗粒缺陷的减少。 因此，本发明公开了一种用于以显着节省浆料使用的方式间歇地将浆料输送到化学机械抛光装置的方法和系统。

    Methods for Minimizing Edge Peeling in the Manufacturing of BSI Chips
    10.
    发明申请
    Methods for Minimizing Edge Peeling in the Manufacturing of BSI Chips 有权
    在BSI芯片制造中最小化边缘剥离的方法

    公开(公告)号：US20140024170A1

    公开(公告)日：2014-01-23

    申请号：US13551457

    申请日：2012-07-17

    申请人： Chun-Ting Kuo ,  Kei-Wei Chen ,  Ying-Lang Wang ,  Kuo-Hsiu Wei

    发明人： Chun-Ting Kuo ,  Kei-Wei Chen ,  Ying-Lang Wang ,  Kuo-Hsiu Wei

    IPC分类号： H01L31/18

    CPC分类号： H01L27/1464 ,  H01L21/02087 ,  H01L21/0209 ,  H01L27/14687

    摘要： A method includes forming top metal lines over a semiconductor substrate, wherein the semiconductor substrate is a portion of a wafer having a bevel. When the top metal lines are exposed, an etchant is supplied on the bevel, wherein regions of the wafer sprayed with the etchant has an inner defining line forming a first ring having a first diameter. A trimming step is performed to trim an edge portion of the wafer, wherein an edge of a remaining portion of the wafer has a second diameter substantially equal to or smaller than the first diameter.

    摘要翻译： 一种方法包括在半导体衬底上形成顶部金属线，其中半导体衬底是具有斜面的晶片的一部分。 当顶部金属线暴露时，在斜面上提供蚀刻剂，其中用蚀刻剂喷射的晶片的区域具有形成具有第一直径的第一环的内部限定线。 进行修整步骤以修剪晶片的边缘部分，其中晶片的剩余部分的边缘具有基本上等于或小于第一直径的第二直径。