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    Preventing silicide formation at the gate electrode in a replacement metal gate technology
    3.
    发明授权
    Preventing silicide formation at the gate electrode in a replacement metal gate technology 失效
    在替代金属栅极技术中防止栅电极处的硅化物形成

    公开(公告)号：US07754552B2

    公开(公告)日：2010-07-13

    申请号：US10629127

    申请日：2003-07-29

    申请人： Chris E. Barns ,  Justin K. Brask ,  Mark Doczy

    发明人： Chris E. Barns ,  Justin K. Brask ,  Mark Doczy

    IPC分类号： H01L21/338

    CPC分类号： H01L29/66545

    摘要： A hard mask may be formed and maintained over a polysilicon gate structure in a metal gate replacement technology. The maintenance of the hard mask, such as a nitride hard mask, may protect the polysilicon gate structure 14 from the formation of silicide or etch byproducts. Either the silicide or the etch byproducts or their combination may block the ensuing polysilicon etch which is needed to remove the polysilicon gate structure and to thereafter replace it with an appropriate metal gate technology.

    摘要翻译： 在金属栅极替换技术中，可以在多晶硅栅极结构上形成并保持硬掩模。 硬掩模（例如氮化物硬掩模）的维护可以保护多晶硅栅极结构14免受硅化物或蚀刻副产物的形成。 硅化物或蚀刻副产物或它们的组合可以阻止除去多晶硅栅极结构所需的随后的多晶硅蚀刻，然后用适当的金属栅极技术代替它。

    Method of forming a metal oxide dielectric
    7.
    发明授权
    Method of forming a metal oxide dielectric 有权
    形成金属氧化物电介质的方法

    公开(公告)号：US07326656B2

    公开(公告)日：2008-02-05

    申请号：US11362453

    申请日：2006-02-24

    申请人： Justin K. Brask ,  Brian S. Doyle ,  Jack Kavalleros ,  Mark Doczy ,  Uday Shah ,  Robert S. Chau

    发明人： Justin K. Brask ,  Brian S. Doyle ,  Jack Kavalleros ,  Mark Doczy ,  Uday Shah ,  Robert S. Chau

    IPC分类号： H01L21/31

    CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  Y10S438/926 ,  Y10S438/974

    摘要： A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

    摘要翻译： 要求保护半导体器件，该半导体器件具有形成在绝缘衬底上的具有顶表面和第一和第二横向相对侧壁的半导体本体。 在半导体本体的顶表面和半导体本体的第一和第二横向相对的侧壁上形成栅极电介质。 然后在半导体主体的顶表面上的栅电介质上形成栅电极，并且与半导体本体的第一和第二横向相对的侧壁上的栅电介质相邻。 栅电极包括直接与栅介电层相邻形成的金属膜。 然后在栅电极的相对侧上的半导体本体中形成一对源区和漏区。

    METHOD OF FORMING A NONPLANAR TRANSISTOR WITH SIDEWALL SPACERS
    8.
    发明申请
    METHOD OF FORMING A NONPLANAR TRANSISTOR WITH SIDEWALL SPACERS 审中-公开
    形成非平面晶体管的方法

    公开(公告)号：US20090149012A1

    公开(公告)日：2009-06-11

    申请号：US12369642

    申请日：2009-02-11

    申请人： Justin K. Brask ,  Brian S. Doyle ,  Jack Kavalieros ,  Mark Doczy ,  Uday Shah ,  Robert S. Chau

    发明人： Justin K. Brask ,  Brian S. Doyle ,  Jack Kavalieros ,  Mark Doczy ,  Uday Shah ,  Robert S. Chau

    IPC分类号： H01L21/4763

    CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  Y10S438/926 ,  Y10S438/974

    摘要： A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

    摘要翻译： 要求保护半导体器件，该半导体器件具有形成在绝缘衬底上的具有顶表面和第一和第二横向相对侧壁的半导体本体。 在半导体本体的顶表面和半导体本体的第一和第二横向相对的侧壁上形成栅极电介质。 然后在半导体主体的顶表面上的栅电介质上形成栅电极，并且与半导体本体的第一和第二横向相对的侧壁上的栅电介质相邻。 栅电极包括直接与栅介电层相邻形成的金属膜。 然后在栅电极的相对侧上的半导体本体中形成一对源区和漏区。

    Nonplanar transistors with metal gate electrodes
    10.
    发明授权
    Nonplanar transistors with metal gate electrodes 有权
    具有金属栅电极的非平面晶体管

    公开(公告)号：US07528025B2

    公开(公告)日：2009-05-05

    申请号：US11986510

    申请日：2007-11-21

    申请人： Justin K. Brask ,  Brian S. Dovle ,  Jack Kavalleros ,  Mark Doczy ,  Uday Shah ,  Robert S. Chau

    发明人： Justin K. Brask ,  Brian S. Dovle ,  Jack Kavalleros ,  Mark Doczy ,  Uday Shah ,  Robert S. Chau

    IPC分类号： H01L21/338

    CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  Y10S438/926 ,  Y10S438/974

    摘要： A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

    摘要翻译： 要求保护半导体器件，该半导体器件具有形成在绝缘衬底上的具有顶表面和第一和第二横向相对侧壁的半导体本体。 在半导体本体的顶表面和半导体本体的第一和第二横向相对的侧壁上形成栅极电介质。 然后在半导体主体的顶表面上的栅电介质上形成栅电极，并且与半导体本体的第一和第二横向相对的侧壁上的栅电介质相邻。 栅电极包括直接与栅介电层相邻形成的金属膜。 然后在栅电极的相对侧上的半导体本体中形成一对源区和漏区。