公开(公告)号：US07528025B2

公开(公告)日：2009-05-05

申请号：US11986510

申请日：2007-11-21

申请人： Justin K. Brask ,  Brian S. Dovle ,  Jack Kavalleros ,  Mark Doczy ,  Uday Shah ,  Robert S. Chau

发明人： Justin K. Brask ,  Brian S. Dovle ,  Jack Kavalleros ,  Mark Doczy ,  Uday Shah ,  Robert S. Chau

IPC分类号： H01L21/338

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  Y10S438/926 ,  Y10S438/974

摘要： A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

摘要翻译： 要求保护半导体器件，该半导体器件具有形成在绝缘衬底上的具有顶表面和第一和第二横向相对侧壁的半导体本体。 在半导体本体的顶表面和半导体本体的第一和第二横向相对的侧壁上形成栅极电介质。 然后在半导体主体的顶表面上的栅电介质上形成栅电极，并且与半导体本体的第一和第二横向相对的侧壁上的栅电介质相邻。 栅电极包括直接与栅介电层相邻形成的金属膜。 然后在栅电极的相对侧上的半导体本体中形成一对源区和漏区。

公开(公告)号：US07326656B2

公开(公告)日：2008-02-05

申请号：US11362453

申请日：2006-02-24

申请人： Justin K. Brask ,  Brian S. Doyle ,  Jack Kavalleros ,  Mark Doczy ,  Uday Shah ,  Robert S. Chau

发明人： Justin K. Brask ,  Brian S. Doyle ,  Jack Kavalleros ,  Mark Doczy ,  Uday Shah ,  Robert S. Chau

IPC分类号： H01L21/31

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  Y10S438/926 ,  Y10S438/974

摘要： A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

摘要翻译： 要求保护半导体器件，该半导体器件具有形成在绝缘衬底上的具有顶表面和第一和第二横向相对侧壁的半导体本体。 在半导体本体的顶表面和半导体本体的第一和第二横向相对的侧壁上形成栅极电介质。 然后在半导体主体的顶表面上的栅电介质上形成栅电极，并且与半导体本体的第一和第二横向相对的侧壁上的栅电介质相邻。 栅电极包括直接与栅介电层相邻形成的金属膜。 然后在栅电极的相对侧上的半导体本体中形成一对源区和漏区。

公开(公告)号：US07531437B2

公开(公告)日：2009-05-12

申请号：US11360269

申请日：2006-02-22

申请人： Justin K. Brask ,  Brian S. Doyle ,  Jack Kavalieros ,  Mark Doczy ,  Uday Shah ,  Robert S. Chau

发明人： Justin K. Brask ,  Brian S. Doyle ,  Jack Kavalieros ,  Mark Doczy ,  Uday Shah ,  Robert S. Chau

IPC分类号： H01L21/3205

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  Y10S438/926 ,  Y10S438/974

摘要： A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

摘要翻译： 要求保护半导体器件，该半导体器件具有形成在绝缘衬底上的具有顶表面和第一和第二横向相对侧壁的半导体本体。 在半导体本体的顶表面和半导体本体的第一和第二横向相对的侧壁上形成栅极电介质。 然后在半导体主体的顶表面上的栅电介质上形成栅电极，并且与半导体本体的第一和第二横向相对的侧壁上的栅电介质相邻。 栅电极包括直接与栅介电层相邻形成的金属膜。 然后在栅电极的相对侧上的半导体本体中形成一对源区和漏区。

公开(公告)号：US20090149012A1

公开(公告)日：2009-06-11

申请号：US12369642

申请日：2009-02-11

申请人： Justin K. Brask ,  Brian S. Doyle ,  Jack Kavalieros ,  Mark Doczy ,  Uday Shah ,  Robert S. Chau

发明人： Justin K. Brask ,  Brian S. Doyle ,  Jack Kavalieros ,  Mark Doczy ,  Uday Shah ,  Robert S. Chau

IPC分类号： H01L21/4763

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  Y10S438/926 ,  Y10S438/974

摘要： A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

摘要翻译： 要求保护半导体器件，该半导体器件具有形成在绝缘衬底上的具有顶表面和第一和第二横向相对侧壁的半导体本体。 在半导体本体的顶表面和半导体本体的第一和第二横向相对的侧壁上形成栅极电介质。 然后在半导体主体的顶表面上的栅电介质上形成栅电极，并且与半导体本体的第一和第二横向相对的侧壁上的栅电介质相邻。 栅电极包括直接与栅介电层相邻形成的金属膜。 然后在栅电极的相对侧上的半导体本体中形成一对源区和漏区。

公开(公告)号：US07361958B2

公开(公告)日：2008-04-22

申请号：US10956279

申请日：2004-09-30

申请人： Justin K. Brask ,  Brian S. Doyle ,  Jack Kavalieros ,  Mark Doczy ,  Uday Shah ,  Robert S. Chau

发明人： Justin K. Brask ,  Brian S. Doyle ,  Jack Kavalieros ,  Mark Doczy ,  Uday Shah ,  Robert S. Chau

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  Y10S438/926 ,  Y10S438/974

摘要： A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

公开(公告)号：US20090020825A1

公开(公告)日：2009-01-22

申请号：US12283217

申请日：2008-09-10

申请人： Mark Doczy ,  Mitchell Taylor ,  Justin K. Brask ,  Jack Kavalieros ,  Suman Datta ,  Matthew V. Metz ,  Robert S. Chau ,  Jack Hwang

发明人： Mark Doczy ,  Mitchell Taylor ,  Justin K. Brask ,  Jack Kavalieros ,  Suman Datta ,  Matthew V. Metz ,  Robert S. Chau ,  Jack Hwang

IPC分类号： H01L27/092

CPC分类号： H01L21/823842

摘要： Complementary metal oxide semiconductor metal gate transistors may be formed by depositing a metal layer in trenches formerly inhabited by patterned gate structures. The patterned gate structures may have been formed of polysilicon in one embodiment. The metal layer may have a workfunction most suitable for forming one type of transistor, but is used to form both the n and p-type transistors. The workfunction of the metal layer may be converted, for example, by ion implantation to make it more suitable for use in forming transistors of the opposite type.

摘要翻译： 互补金属氧化物半导体金属栅极晶体管可以通过在先前由图案化栅极结构居住的沟槽中沉积金属层来形成。 在一个实施例中，图案化栅极结构可以由多晶硅形成。 金属层可以具有最适于形成一种类型的晶体管的功函数，但是用于形成n型和p型晶体管。 可以例如通过离子注入来转换金属层的功函数，使其更适用于形成相反类型的晶体管。

公开(公告)号：US07439113B2

公开(公告)日：2008-10-21

申请号：US10889535

申请日：2004-07-12

申请人： Mark Doczy ,  Mitchell Taylor ,  Justin K. Brask ,  Jack Kavalieros ,  Suman Datta ,  Matthew V. Metz ,  Robert S. Chau ,  Jack Hwang

发明人： Mark Doczy ,  Mitchell Taylor ,  Justin K. Brask ,  Jack Kavalieros ,  Suman Datta ,  Matthew V. Metz ,  Robert S. Chau ,  Jack Hwang

IPC分类号： H01L29/78

CPC分类号： H01L21/823842

摘要： Complementary metal oxide semiconductor metal gate transistors may be formed by depositing a metal layer in trenches formerly inhabited by patterned gate structures. The patterned gate structures may have been formed of polysilicon in one embodiment. The metal layer may have a workfunction most suitable for forming one type of transistor, but is used to form both the n and p-type transistors. The workfunction of the metal layer may be converted, for example, by ion implantation to make it more suitable for use in forming transistors of the opposite type.

摘要翻译： 互补金属氧化物半导体金属栅极晶体管可以通过在先前由图案化栅极结构居住的沟槽中沉积金属层来形成。 在一个实施例中，图案化栅极结构可以由多晶硅形成。 金属层可以具有最适于形成一种类型的晶体管的功函数，但是用于形成n型和p型晶体管。 可以例如通过离子注入来转换金属层的功函数，使其更适用于形成相反类型的晶体管。

公开(公告)号：US07192856B2

公开(公告)日：2007-03-20

申请号：US11037860

申请日：2005-01-18

申请人： Mark Doczy ,  Lawrence D. Wong ,  Valery M. Dubin ,  Justin K. Brask ,  Jack Kavalieros ,  Suman Datta ,  Matthew V. Metz ,  Robert S. Chau

发明人： Mark Doczy ,  Lawrence D. Wong ,  Valery M. Dubin ,  Justin K. Brask ,  Jack Kavalieros ,  Suman Datta ,  Matthew V. Metz ,  Robert S. Chau

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： Complementary metal oxide semiconductor metal gate transistors may be formed by depositing a metal layer in trenches formerly inhabited by patterned gate structures. The patterned gate structures may have been formed of polysilicon in one embodiment. The trenches may be filled with metal by surface activating using a catalytic metal, followed by electroless deposition of a seed layer followed by superconformal filling bottom up.

摘要翻译： 互补金属氧化物半导体金属栅极晶体管可以通过在先前由图案化栅极结构居住的沟槽中沉积金属层来形成。 在一个实施例中，图案化栅极结构可以由多晶硅形成。 可以使用催化金属通过表面活化来填充沟槽，然后通过化学沉积种子层，然后从底部向上填充超融合填充物。

公开(公告)号：US20080090397A1

公开(公告)日：2008-04-17

申请号：US11986510

申请日：2007-11-21

申请人： Justin Brask ,  Brian Dovle ,  Jack Kavalleros ,  Mark Doczy ,  Uday Shah ,  Robert Chau

发明人： Justin Brask ,  Brian Dovle ,  Jack Kavalleros ,  Mark Doczy ,  Uday Shah ,  Robert Chau

IPC分类号： H01L21/3205

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  Y10S438/926 ,  Y10S438/974

摘要： A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

摘要翻译： 要求保护半导体器件，该半导体器件具有形成在绝缘衬底上的具有顶表面和第一和第二横向相对侧壁的半导体本体。 在半导体本体的顶表面和半导体本体的第一和第二横向相对的侧壁上形成栅极电介质。 然后在半导体主体的顶表面上的栅电介质上形成栅电极，并且与半导体本体的第一和第二横向相对的侧壁上的栅电介质相邻。 栅电极包括直接与栅介电层相邻形成的金属膜。 然后在栅电极的相对侧上的半导体本体中形成一对源区和漏区。

公开(公告)号：US20060138553A1

公开(公告)日：2006-06-29

申请号：US11362453

申请日：2006-02-24

申请人： Justin Brask ,  Brian Doyle ,  Jack Kavalleros ,  Mark Doczy ,  Uday Shah ,  Robert Chau

发明人： Justin Brask ,  Brian Doyle ,  Jack Kavalleros ,  Mark Doczy ,  Uday Shah ,  Robert Chau

IPC分类号： H01L29/94

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  Y10S438/926 ,  Y10S438/974

摘要： A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.