公开(公告)号：US06285220B1

公开(公告)日：2001-09-04

申请号：US09633421

申请日：2000-08-04

申请人： Christophe Gaillard ,  Stéphane Le Tual

发明人： Christophe Gaillard ,  Stéphane Le Tual

IPC分类号： G11C2702

CPC分类号： G11C27/024

摘要： A sample-and-hold device comprises a sampling transistor (Qech) and a sampling capacitor (Cech), the sampling transistor being off in hold mode in order to prevent the discharging of the sampling capacitor and conductive in sampling mode to apply a voltage to the capacitor that is substantially equal to the voltage (Vech) at its base. In order to apply a cut-off voltage to this base, in off mode, that is equal to the voltage present at the sampling capacitor, there is provided a circuit comprising, in series, between two power supply terminals, two MOS type transistors (MP1, MP2) having drain-source channels substantially with the same width-to-length ratio, a bipolar transistor (Qcl) having its base connected to the junction point of the two MOS transistors and its emitter connected to the base of the sampling transistor (Qech), and a diode (D1) biased by a current (Ip), connected between the source and the gate of one of the two MOS transistors (MP1), the gate of the other transistor (MP2) being connected to the sampling capacitor. This device can be applied especially to samplers used upline to an analog-digital converter.

摘要翻译： 采样保持装置包括采样晶体管（Qech）和采样电容器（Cech），采样晶体管处于保持模式，以防止采样电容器的放电和采样模式下导通，以将电压施加到 该电容器基本上等于其基极处的电压（Vech）。 为了对该基极施加截止电压，在关断模式下，等于采样电容器上存在的电压，提供了一种电路，其串联包括两个电源端子，两个MOS型晶体管（ 具有漏极 - 源极通道基本上具有相同的宽度 - 长度比的双极晶体管（Qcl），其基极连接到两个MOS晶体管的连接点，其发射极连接到采样晶体管的基极 （Qech）和连接在两个MOS晶体管（MP1）之一的源极和栅极之间的由电流（Ip）偏置的二极管（D1），另一个晶体管（MP2）的栅极连接到采样 电容器。 该器件可以特别适用于使用模拟数字转换器上行线路的采样器。

公开(公告)号：US06346904B1

公开(公告)日：2002-02-12

申请号：US09635765

申请日：2000-08-11

申请人： Christophe Gaillard ,  Marc Wingender ,  Stéphane Le Tual

发明人： Christophe Gaillard ,  Marc Wingender ,  Stéphane Le Tual

IPC分类号： H03M112

CPC分类号： H03M1/445

摘要： A signal aliasing circuit that can be used especially to make a series interpolation cell of an interpolation analog-digital converter comprises two pairs of differential arms powered by one and the same current source connected to a first power supply terminal, each pair comprising two transistors, the transistors of one pair being parallel-connected with the transistors of the other pair. Each group of two parallel-connected transistors is connected by a respective common resistor to a second power supply terminal, the two outputs of the aliasing circuit being the combined collectors of the two groups of parallel-connected transistors. The disclosed device can be applied especially to converters whose architecture comprises what is known as a series interpolation part requiring high precision.

摘要翻译： 可以特别用于制作插值模拟数字转换器的串联插补单元的信号混叠电路包括由连接到第一电源端子的同一个电流源供电的两对差分臂，每对包含两个晶体管， 一对的晶体管与另一对的晶体管并联连接。 两个并联连接的晶体管的每组由相应的公共电阻器连接到第二电源端子，混叠电路的两个输出是两组并联晶体管的组合集电极。 所公开的装置可以特别应用于其架构包括所谓的要求高精度的串联插补部件的转换器。

公开(公告)号：US20100171548A1

公开(公告)日：2010-07-08

申请号：US12690793

申请日：2010-01-20

申请人： Eoin Ohannaidh ,  Stéphane Le Tual ,  Loïc Joet

发明人： Eoin Ohannaidh ,  Stéphane Le Tual ,  Loïc Joet

IPC分类号： H03K5/00

CPC分类号： H03H15/02 ,  H03H11/1291

摘要： An analog finite impulse response (AFIR) filter including at least one variable transconductance block having an input for receiving an input voltage and being adapted to sequentially apply each of a plurality of transconductance levels to the input voltage during at least one of a plurality of successive time periods to generate an output current at an output of the variable transconductance block, the at least one variable transconductance block including a plurality of fixed transconductance blocks each receiving the input voltage and capable of being independently activated to supply the output current; and a capacitor coupled to the output of the variable transconductance block to receive the output current and provide an output voltage of the filter.

摘要翻译： 一种模拟有限脉冲响应（AFIR）滤波器，包括至少一个可变跨导块，其具有用于接收输入电压的输入，并且适于在多个连续的至少一个期间顺序地将多个跨导电平中的每一个施加到输入电压 在所述可变跨导块的输出处产生输出电流的所述时间周期，所述至少一个可变跨导块包括多个固定跨导块，每个固定跨导块接收所述输入电压并且能够被独立地激活以提供所述输出电流; 以及耦合到可变跨导块的输出的电容器，以接收输出电流并提供滤波器的输出电压。

公开(公告)号：US07652613B2

公开(公告)日：2010-01-26

申请号：US12015039

申请日：2008-01-16

申请人： Loïc Joet ,  Stéphane Le Tual

发明人： Loïc Joet ,  Stéphane Le Tual

IPC分类号： H03M1/12

CPC分类号： H03M1/0629 ,  H03M1/0682 ,  H03M1/1023 ,  H03M1/1215 ,  H03M1/46

摘要： The method and device include the filtering and the analog/digital conversion of an intermediate signal. The intermediate signal is processed by a filtering and analog/digital conversion circuit that is configurable using switched passive capacitor technology. The various configurations successively adopted by the circuit provide filtering and analog/digital conversion to be successively carried out.

摘要翻译： 该方法和装置包括中间信号的滤波和模拟/数字转换。 中间信号由可使用切换无源电容技术配置的滤波和模拟/数字转换电路进行处理。 电路连续采用的各种配置提供了连续进行的滤波和模/数转换。

公开(公告)号：US08497795B2

公开(公告)日：2013-07-30

申请号：US13166117

申请日：2011-06-22

申请人： Stéphane Le Tual ,  Pratap Narayan Singh ,  Oleksiy Zabroda ,  Nicola Vannucci

发明人： Stéphane Le Tual ,  Pratap Narayan Singh ,  Oleksiy Zabroda ,  Nicola Vannucci

IPC分类号： H03M1/34

CPC分类号： H03M1/468

摘要： A differential successive approximation analog to digital converter including: a comparator; a first plurality of capacitors coupled between a corresponding plurality of first switches and a first input of the comparator, at least one of the first capacitors being arranged to receive a first component of a differential input signal; and a second plurality of capacitors coupled between a corresponding plurality of second switches and a second input of the comparator, at least one of the second capacitors being arranged to receive a second component of the differential input signal, wherein each of the first and second plurality of switches are each adapted to independently couple the corresponding capacitor to a selected one of: a first supply voltage level; a second supply voltage level; and a third supply voltage level; and control circuitry adapted to sample the differential input voltage during a sample phase, and to control the first and second switches to couple each capacitor of the first and second plurality of capacitors to the third supply voltage level at the start of a voltage conversion phase.

摘要翻译： 一种差分逐次逼近模数转换器，包括：比较器; 耦合在对应的多个第一开关和比较器的第一输入之间的第一多个电容器，所述第一电容器中的至少一个被布置为接收差分输入信号的第一分量; 以及耦合在相应的多个第二开关和所述比较器的第二输入之间的第二多个电容器，所述第二电容器中的至少一个布置成接收所述差分输入信号的第二分量，其中所述第一和第二多个 的开关各自适于独立地将相应的电容器耦合到所选择的一个：第一电源电压电平; 第二电源电压; 和第三电源电压电平; 以及控制电路，其适于在采样阶段期间对差分输入电压进行采样，并且控制第一和第二开关以在电压转换阶段开始时将第一和第二多个电容器的每个电容器耦合到第三电源电压电平。

公开(公告)号：US08378727B2

公开(公告)日：2013-02-19

申请号：US13166608

申请日：2011-06-22

申请人： Pratap Narayan Singh ,  Stéphane Le Tual

发明人： Pratap Narayan Singh ,  Stéphane Le Tual

IPC分类号： H03K3/00

CPC分类号： H03K3/356043 ,  H03K3/012 ,  H03K3/356078

摘要： A common-source circuit including two branches in parallel between a terminal of application of a voltage and a current source, each branch comprising: a series association of a resistor and a transistor, having their junction point defining an output terminal of the branch; a first switch connecting an input terminal of the branch to a control terminal of the transistor; and a controllable stage for amplifying data representing the level present on the output terminal of the opposite branch.

摘要翻译： 一种公共源电路，包括在施加电压的端子和电流源之间并联的两个分支，每个分支包括：电阻器和晶体管的串联关联，其连接点限定所述分支的输出端子; 将所述分支的输入端子连接到所述晶体管的控制端子的第一开关; 以及用于放大表示相对分支的输出端子上存在的电平的数据的可控级。

公开(公告)号：US20120286832A1

公开(公告)日：2012-11-15

申请号：US13300318

申请日：2011-11-18

申请人： Stéphane Le Tual ,  Pratap Singh

发明人： Stéphane Le Tual ,  Pratap Singh

IPC分类号： H03L7/00

CPC分类号： G06F13/423

摘要： The invention concerns a circuit comprising: a first circuit block (302) adapted to receive a first clock signal (CLK1) and to provide a first output data signal at a time determined by said first clock signal; a second circuit block (304) adapted to receive a second clock signal (CLK2) and to provide a second output data signal at a time determined by said second clock signal; a clock bus (314) coupled to corresponding outputs of said first and second circuit blocks for receiving a third clock signal (BCLK) based on said first and second clock signals; and a synchronization unit (312) coupled to said clock bus and adapted to sample said first and second output data signals based on said third clock signal.

摘要翻译： 本发明涉及一种电路，包括：适于接收第一时钟信号（CLK1）并在由所述第一时钟信号确定的时间提供第一输出数据信号的第一电路块（302） 适于接收第二时钟信号（CLK2）并在由所述第二时钟信号确定的时间提供第二输出数据信号的第二电路块（304） 连接到所述第一和第二电路块的相应输出的时钟总线（314），用于基于所述第一和第二时钟信号接收第三时钟信号（BCLK）; 以及耦合到所述时钟总线并适于基于所述第三时钟信号对所述第一和第二输出数据信号进行采样的同步单元（312）。

公开(公告)号：US20110316587A1

公开(公告)日：2011-12-29

申请号：US13166608

申请日：2011-06-22

申请人： Pratap Narayan Singh ,  Stéphane Le Tual

发明人： Pratap Narayan Singh ,  Stéphane Le Tual

IPC分类号： H03K5/22

CPC分类号： H03K3/356043 ,  H03K3/012 ,  H03K3/356078

摘要： A common-source circuit including two branches in parallel between a terminal of application of a voltage and a current source, each branch comprising: a series association of a resistor and a transistor, having their junction point defining an output terminal of the branch; a first switch connecting an input terminal of the branch to a control terminal of the transistor; and a controllable stage for amplifying data representing the level present on the output terminal of the opposite branch.

摘要翻译： 一种公共源电路，包括在施加电压的端子和电流源之间并联的两个分支，每个分支包括：电阻器和晶体管的串联关联，其连接点限定所述分支的输出端子; 将所述分支的输入端子连接到所述晶体管的控制端子的第一开关; 以及用于放大表示相对分支的输出端子上存在的电平的数据的可控级。

公开(公告)号：US09298666B2

公开(公告)日：2016-03-29

申请号：US13300318

申请日：2011-11-18

申请人： Stéphane Le Tual ,  Pratap Singh

发明人： Stéphane Le Tual ,  Pratap Singh

IPC分类号： H04L7/00 ,  G06F13/42

CPC分类号： G06F13/423

摘要： The invention concerns a circuit comprising: a first circuit block (302) adapted to receive a first clock signal (CLK1) and to provide a first output data signal at a time determined by said first clock signal; a second circuit block (304) adapted to receive a second clock signal (CLK2) and to provide a second output data signal at a time determined by said second clock signal; a clock bus (314) coupled to corresponding outputs of said first and second circuit blocks for receiving a third clock signal (BCLK) based on said first and second clock signals; and a synchronization unit (312) coupled to said clock bus and adapted to sample said first and second output data signals based on said third clock signal.

摘要翻译： 本发明涉及一种电路，包括：适于接收第一时钟信号（CLK1）并在由所述第一时钟信号确定的时间提供第一输出数据信号的第一电路块（302） 适于接收第二时钟信号（CLK2）并在由所述第二时钟信号确定的时间提供第二输出数据信号的第二电路块（304） 连接到所述第一和第二电路块的相应输出的时钟总线（314），用于基于所述第一和第二时钟信号接收第三时钟信号（BCLK）; 以及耦合到所述时钟总线并适于基于所述第三时钟信号对所述第一和第二输出数据信号进行采样的同步单元（312）。

公开(公告)号：US08514123B2

公开(公告)日：2013-08-20

申请号：US13247001

申请日：2011-09-28

申请人： Stéphane Le Tual ,  Mounir Boulemnakher ,  Pratap Narayan Singh

发明人： Stéphane Le Tual ,  Mounir Boulemnakher ,  Pratap Narayan Singh

IPC分类号： H03M1/34

CPC分类号： H03M1/468

摘要： A method of successive approximation analog to digital conversion including: during a sample phase, coupling an input signal to a plurality of pairs of capacitors; and during a conversion phase, coupling a first capacitor of each pair to a first supply voltage, and a second capacitor of each pair to a second supply voltage.

摘要翻译： 一种逐次逼近模数转换的方法，包括：在采样阶段期间，将输入信号耦合到多对电容器; 并且在转换阶段期间，将每对的第一电容器耦合到第一电源电压，将每对的第二电容器耦合到第二电源电压。