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    Semiconductor chip package and method for fabricating semiconductor chip
    1.
    发明申请
    Semiconductor chip package and method for fabricating semiconductor chip 有权
    半导体芯片封装及制造半导体芯片的方法

    公开(公告)号：US20080204091A1

    公开(公告)日：2008-08-28

    申请号：US12072401

    申请日：2008-02-26

    申请人： Chul-Hwan Choo ,  Hi-Choon Lee ,  Young-Yong Byun

    发明人： Chul-Hwan Choo ,  Hi-Choon Lee ,  Young-Yong Byun

    IPC分类号： H03L7/08 ,  H01L23/12

    CPC分类号： H03L7/0812 ,  G11C5/02 ,  G11C5/04 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01055 ,  H01L2924/15311 ,  H03L7/0814 ,  H01L2224/0401

    摘要： A semiconductor chip package and a semiconductor chip fabricating method are provided. A semiconductor chip package comprises at least two semiconductor chips having a stacked configuration, the semiconductor chips at least one of: sharing DC signals of DC generating circuits provided by one of the semiconductor chips; and sharing a DLL clock signal of a DLL circuit provided by the semiconductor chip having the DC generating circuits or provided by another semiconductor chip. Power consumption can be reduced, and sharing a DLL clock is valid. In addition, a stabilized DC supply can be guaranteed and an increase for level trimming range and productivity can be improved.

    摘要翻译： 提供半导体芯片封装和半导体芯片制造方法。 半导体芯片封装包括至少两个具有堆叠结构的半导体芯片，所述半导体芯片至少一个：共享由所述半导体芯片中的一个提供的直流发电电路的直流信号; 并且共享由具有DC发生电路的半导体芯片提供或由另一半导体芯片提供的DLL电路的DLL电路的DLL时钟信号。 可以减少功耗，共享DLL时钟是有效的。 此外，可以保证稳定的DC电源，并且可以提高修整范围和生产率的增加。

    Die packages and systems having the die packages
    3.
    发明授权
    Die packages and systems having the die packages 有权
    具有管芯封装的管芯封装和系统

    公开(公告)号：US08710655B2

    公开(公告)日：2014-04-29

    申请号：US13546517

    申请日：2012-07-11

    申请人： Hyun-Joong Kim ,  Jang Seok Choi ,  Chul-Hwan Choo

    发明人： Hyun-Joong Kim ,  Jang Seok Choi ,  Chul-Hwan Choo

    IPC分类号： H01L23/48 ,  H05K7/20

    CPC分类号： H01L25/0652 ,  H01L24/16 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/1301 ,  H01L2924/15311 ,  H01L2924/00

    摘要： A die package may include a package substrate; an interposer; and/or at least one first die connected between the package substrate and the interposer. The die package may further include at least one second die mounted on the interposer and/or a processor. A system may include a system board and/or a die package mounted on the system board. The die package may include a package substrate; an interposer; and/or at least one first die connected between the package substrate and the interposer. The system may further include at least one second die mounted on the interposer and/or a processor. The processor may control data processing operations of the at least one first die and/or the at least one second die.

    摘要翻译： 管芯封装可以包括封装衬底; 中介者 和/或连接在封装衬底和插入件之间的至少一个第一管芯。 管芯封装还可包括安装在插入件和/或处理器上的至少一个第二管芯。 系统可以包括安装在系统板上的系统板和/或管芯封装。 管芯封装可以包括封装衬底; 中介者 和/或连接在封装衬底和插入件之间的至少一个第一管芯。 系统还可以包括安装在插入器和/或处理器上的至少一个第二裸片。 处理器可以控制至少一个第一管芯和/或至少一个第二管芯的数据处理操作。

    DIE PACKAGES AND SYSTEMS HAVING THE DIE PACKAGES
    4.
    发明申请
    DIE PACKAGES AND SYSTEMS HAVING THE DIE PACKAGES 有权
    DIE包和DIES包的系统

    公开(公告)号：US20130161812A1

    公开(公告)日：2013-06-27

    申请号：US13546517

    申请日：2012-07-11

    申请人： Hyun-Joong Kim ,  Jang Seok Choi ,  Chul-Hwan Choo

    发明人： Hyun-Joong Kim ,  Jang Seok Choi ,  Chul-Hwan Choo

    IPC分类号： H01L23/48

    CPC分类号： H01L25/0652 ,  H01L24/16 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/1301 ,  H01L2924/15311 ,  H01L2924/00

    摘要： A die package may include a package substrate; an interposer; and/or at least one first die connected between the package substrate and the interposer. The die package may further include at least one second die mounted on the interposer and/or a processor. A system may include a system board and/or a die package mounted on the system board. The die package may include a package substrate; an interposer; and/or at least one first die connected between the package substrate and the interposer. The system may further include at least one second die mounted on the interposer and/or a processor. The processor may control data processing operations of the at least one first die and/or the at least one second die.

    摘要翻译： 管芯封装可以包括封装衬底; 中介者 和/或连接在封装衬底和插入件之间的至少一个第一管芯。 管芯封装还可包括安装在插入件和/或处理器上的至少一个第二管芯。 系统可以包括安装在系统板上的系统板和/或管芯封装。 管芯封装可以包括封装衬底; 中介者 和/或连接在封装衬底和插入件之间的至少一个第一管芯。 系统还可以包括安装在插入器和/或处理器上的至少一个第二裸片。 处理器可以控制至少一个第一管芯和/或至少一个第二管芯的数据处理操作。

    Address converter semiconductor device and semiconductor memory device having the same
    5.
    发明授权
    Address converter semiconductor device and semiconductor memory device having the same 失效
    地址转换器半导体器件及其半导体存储器件

    公开(公告)号：US07319634B2

    公开(公告)日：2008-01-15

    申请号：US11501905

    申请日：2006-08-08

    申请人： Chul-Hwan Choo ,  Ho-Sung Song

    发明人： Chul-Hwan Choo ,  Ho-Sung Song

    IPC分类号： G11C8/00

    CPC分类号： G11C8/18 ,  G11C7/04 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4082 ,  G11C29/18

    摘要： An address converter of a semiconductor device comprises a clock generating portion for generating at least one clock signal when a power voltage is applied; a control signal setting means for setting a control signal during a mode setting operation; a polarity selecting signal generating portion for generating at least one polarity selecting signal in response to the at least one clock signal and the control signal; and an address converting portion for converting at least one bit of an address applied from an external portion to output a converted address in response to the at least one polarity selecting signal.

    摘要翻译： 半导体器件的地址转换器包括时钟产生部分，用于在施加电源电压时产生至少一个时钟信号; 控制信号设定装置，用于在模式设定操作期间设定控制信号; 极性选择信号产生部分，用于响应于至少一个时钟信号和控制信号产生至少一个极性选择信号; 以及地址转换部分，用于转换从外部部分施加的地址的至少一位，以响应于所述至少一个极性选择信号输出转换的地址。

    Address converter semiconductor device and semiconductor memory device having the same
    6.
    发明申请
    Address converter semiconductor device and semiconductor memory device having the same 失效
    地址转换器半导体器件及其半导体存储器件

    公开(公告)号：US20070153619A1

    公开(公告)日：2007-07-05

    申请号：US11501905

    申请日：2006-08-08

    申请人： Chul-Hwan Choo ,  Ho-Sung Song

    发明人： Chul-Hwan Choo ,  Ho-Sung Song

    IPC分类号： G11C8/00

    CPC分类号： G11C8/18 ,  G11C7/04 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4082 ,  G11C29/18

    摘要： An address converter of a semiconductor device comprises a clock generating portion for generating at least one clock signal when a power voltage is applied; a control signal setting means for setting a control signal during a mode setting operation; a polarity selecting signal generating portion for generating at least one polarity selecting signal in response to the at least one clock signal and the control signal; and an address converting portion for converting at least one bit of an address applied from an external portion to output a converted address in response to the at least one polarity selecting signal.

    摘要翻译： 半导体器件的地址转换器包括时钟产生部分，用于在施加电源电压时产生至少一个时钟信号; 控制信号设定装置，用于在模式设定操作期间设定控制信号; 极性选择信号产生部分，用于响应于至少一个时钟信号和控制信号产生至少一个极性选择信号; 以及地址转换部分，用于转换从外部部分施加的地址的至少一位，以响应于所述至少一个极性选择信号输出转换的地址。