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    Multi-chip stack structure and fabricating method thereof
    5.
    发明申请
    Multi-chip stack structure and fabricating method thereof 审中-公开
    多芯片堆叠结构及其制造方法

    公开(公告)号：US20090014860A1

    公开(公告)日：2009-01-15

    申请号：US12011832

    申请日：2008-01-29

    申请人： Chung-Lun Liu ,  Jung-Pin Huang ,  Chin-Huang Chang ,  Chih-Ming Huang ,  Cheng-Hsu Hsiao

    发明人： Chung-Lun Liu ,  Jung-Pin Huang ,  Chin-Huang Chang ,  Chih-Ming Huang ,  Cheng-Hsu Hsiao

    IPC分类号： H01L21/00 ,  H01L23/02

    CPC分类号： H01L25/0652 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/06562 ,  H01L2924/00012

    摘要： A multi-chip stack structure and a manufacturing method thereof are provided. The fabrication method includes the steps of: providing a chip carrier having a first surface and a second surface opposing thereto and at least a first chip and a second chip mounted on the first surface; electrically connecting the chips to the chip carrier by a plurality of bonding wires; and stacking at least a third chip on the first and second chips by a film deposed therebetween, wherein the third chip is stepwise stacked on the first chip and at least a part of the bonding wire connected to the second chip is covered by the film, and electrically connecting the third chip and the chip carrier by a bonding wire, thereby enabling a plurality of chips to be stacked on the chip carrier to enhance the electrical performance of electronic products.

    摘要翻译： 提供了一种多芯片堆叠结构及其制造方法。 该制造方法包括以下步骤：提供具有与其相对的第一表面和第二表面的芯片载体和至少安装在第一表面上的第一芯片和第二芯片; 通过多个接合线将芯片电连接到芯片载体上; 并且通过其间放置的膜将第一和第二芯片上的至少第三芯片堆叠起来，其中第三芯片逐步堆叠在第一芯片上，并且连接到第二芯片的键合线的至少一部分被膜覆盖， 并通过接合线电连接第三芯片和芯片载体，从而能够将多个芯片堆叠在芯片载体上，以增强电子产品的电气性能。

    Fabrication method of multi-chip stack structure
    6.
    发明授权
    Fabrication method of multi-chip stack structure 有权
    多芯片堆叠结构的制作方法

    公开(公告)号：US07981729B2

    公开(公告)日：2011-07-19

    申请号：US12818701

    申请日：2010-06-18

    申请人： Jung-Pin Huang ,  Chin-Huang Chang ,  Chien-Ping Huang ,  Chung-Lun Liu ,  Cheng-Hsu Hsiao

    发明人： Jung-Pin Huang ,  Chin-Huang Chang ,  Chien-Ping Huang ,  Chung-Lun Liu ,  Cheng-Hsu Hsiao

    IPC分类号： H01L21/60

    CPC分类号： H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48496 ,  H01L2224/49175 ,  H01L2224/78 ,  H01L2224/85001 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00

    摘要： A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires. The bump is used for supporting the leads to a certain height so as to keep the bonding wires from contacting the heating block and eliminate the need of using a second heating block in the second wire bonding process of the prior art, thereby saving time and costs in a fabrication process. Also, as positions where the first and second bonding wires are bonded to the leads on opposite sides of the leadframe correspond with each other, the conventional problems of adversely affected electrical performance and electrical mismatch can be prevented.

    摘要翻译： 提出了一种多芯片堆叠结构及其制造方法，包括提供具有芯片基底和多个引线的引线框架，并分别在模具基座的两个表面上设置第一和第二芯片; 将引线框架布置在具有引线接合工艺中的空腔的加热块上，第二芯片容纳在加热块的空腔中; 执行第一引线接合工艺，以通过多个第一接合线将第一芯片电连接到引线，以及在与第一接合线连接的引线的一侧上形成凸块; 通过第一芯片和第一接合线容纳在加热块的空腔中，通过凸块将引线框倒置放置到加热块， 以及执行第二引线接合处理，以通过多个第二接合线将所述第二芯片电连接到所述引线。 凸块用于将引线支撑到一定高度，以便使接合线不会接触加热块，并且在现有技术的第二引线接合过程中不需要使用第二加热块，从而节省了时间和成本 在制造过程中。 此外，由于第一和第二接合线与引线框架的相对侧上的引线接合的位置彼此对应，可以防止电性能和电不匹配受到不利影响的常规问题。

    FABRICATION METHOD OF MULTI-CHIP STACK STRUCTURE
    8.
    发明申请
    FABRICATION METHOD OF MULTI-CHIP STACK STRUCTURE 有权
    多芯片堆叠结构的制作方法

    公开(公告)号：US20100255635A1

    公开(公告)日：2010-10-07

    申请号：US12818701

    申请日：2010-06-18

    申请人： Jung-Pin Huang ,  Chin-Huang Chang ,  Chien-Ping Huang ,  Chung-Lun Liu ,  Cheng-Hsu Hsiao

    发明人： Jung-Pin Huang ,  Chin-Huang Chang ,  Chien-Ping Huang ,  Chung-Lun Liu ,  Cheng-Hsu Hsiao

    IPC分类号： H01L21/60

    CPC分类号： H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48496 ,  H01L2224/49175 ,  H01L2224/78 ,  H01L2224/85001 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00

    摘要： A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires. The bump is used for supporting the leads to a certain height so as to keep the bonding wires from contacting the heating block and eliminate the need of using a second heating block in the second wire bonding process of the prior art, thereby saving time and costs in a fabrication process. Also, as positions where the first and second bonding wires are bonded to the leads on opposite sides of the leadframe correspond with each other, the conventional problems of adversely affected electrical performance and electrical mismatch can be prevented.

    摘要翻译： 提出了一种多芯片堆叠结构及其制造方法，包括提供具有芯片基底和多个引线的引线框架，并分别在模具基座的两个表面上设置第一和第二芯片; 将引线框架布置在具有引线接合工艺中的空腔的加热块上，第二芯片容纳在加热块的空腔中; 执行第一引线接合工艺，以通过多个第一接合线将第一芯片电连接到引线，以及在与第一接合线连接的引线的一侧上形成凸块; 通过第一芯片和第一接合线容纳在加热块的空腔中，通过凸块将引线框倒置放置到加热块， 以及执行第二引线接合处理，以通过多个第二接合线将所述第二芯片电连接到所述引线。 凸块用于将引线支撑到一定高度，以便使接合线不会接触加热块，并且在现有技术的第二引线接合过程中不需要使用第二加热块，从而节省了时间和成本 在制造过程中。 此外，由于第一和第二接合线与引线框架的相对侧上的引线接合的位置彼此对应，可以防止电性能和电不匹配受到不利影响的常规问题。

    Multi-chip stack structure and fabrication method thereof
    9.
    发明申请
    Multi-chip stack structure and fabrication method thereof 有权
    多芯片堆叠结构及其制造方法

    公开(公告)号：US20080224289A1

    公开(公告)日：2008-09-18

    申请号：US12077003

    申请日：2008-03-13

    申请人： Jung-Pin Huang ,  Chin-Huang Chang ,  Chien-Ping Huang ,  Chung-Lun Liu ,  Cheng-Hsu Hsiao

    发明人： Jung-Pin Huang ,  Chin-Huang Chang ,  Chien-Ping Huang ,  Chung-Lun Liu ,  Cheng-Hsu Hsiao

    IPC分类号： H01L23/495 ,  H01L21/00

    CPC分类号： H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48496 ,  H01L2224/49175 ,  H01L2224/78 ,  H01L2224/85001 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00

    摘要： A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires. The bump is used for supporting the leads to a certain height so as to keep the bonding wires from contacting the heating block and eliminate the need of using a second heating block in the second wire bonding process of the prior art, thereby saving time and costs in a fabrication process. Also, as positions where the first and second bonding wires are bonded to the leads on opposite sides of the leadframe correspond with each other, the conventional problems of adversely affected electrical performance and electrical mismatch can be prevented.

    摘要翻译： 提出了一种多芯片堆叠结构及其制造方法，包括提供具有芯片基底和多个引线的引线框架，并分别在模具基座的两个表面上设置第一和第二芯片; 将引线框架布置在具有引线接合工艺中的空腔的加热块上，第二芯片容纳在加热块的空腔中; 执行第一引线接合工艺，以通过多个第一接合线将第一芯片电连接到引线，以及在与第一接合线连接的引线的一侧上形成凸块; 通过第一芯片和第一接合线容纳在加热块的空腔中，通过凸块将引线框倒置放置到加热块， 以及执行第二引线接合处理，以通过多个第二接合线将所述第二芯片电连接到所述引线。 凸块用于将引线支撑到一定高度，以便使接合线不会接触加热块，并且在现有技术的第二引线接合过程中不需要使用第二加热块，从而节省了时间和成本 在制造过程中。 此外，由于第一和第二接合线与引线框架的相对侧上的引线接合的位置彼此对应，可以防止电性能和电不匹配受到不利影响的常规问题。