-
1.发明申请SELECTIVE FIN-SHAPING PROCESS USING PLASMA DOPING AND ETCHING FOR 3-DIMENSIONAL TRANSISTOR APPLICATIONS 有权使用等离子体掺杂和三维晶体管应用蚀刻的选择性熔融成形工艺公开(公告)号：US20130093026A1
公开(公告)日：2013-04-18
申请号：US13273527
申请日：2011-10-14
申请人： Clement Hsingjen WANN , Ling-Yen YEH , Chi-Yuan SHIH , Yi-Tang LIN , Chih-Sheng CHANG , Chi-Wen LIU
发明人： Clement Hsingjen WANN , Ling-Yen YEH , Chi-Yuan SHIH , Yi-Tang LIN , Chih-Sheng CHANG , Chi-Wen LIU
IPC分类号： H01L27/088 , H01L21/762 , H01L29/78
CPC分类号： H01L21/823431 , H01L21/265 , H01L21/31111 , H01L21/76224 , H01L21/823481 , H01L21/823821 , H01L21/845 , H01L27/088 , H01L27/0924 , H01L27/1211 , H01L29/06 , H01L29/66818 , H01L29/78 , H01L29/7853 , H01L29/7854
摘要： A semiconductor apparatus includes fin field-effect transistor (FinFETs) having shaped fins and regular fins. Shaped fins have top portions that may be smaller, larger, thinner, or shorter than top portions of regular fins. The bottom portions of shaped fins and regular fins are the same. FinFETs may have only one or more shaped fins, one or more regular fins, or a mixture of shaped fins and regular fins. A semiconductor manufacturing process to shape one fin includes forming a photolithographic opening of one fin, optionally doping a portion of the fin, and etching a portion of the fin.
摘要翻译： 半导体装置包括具有成形翅片和规则翅片的鳍状场效应晶体管（FinFET）。 成形翅片的顶部可以比普通翅片的顶部更小，更大，更薄或更短。 成形翅片和规则翅片的底部是相同的。 FinFET可以仅具有一个或多个成形翅片，一个或多个规则翅片，或者成形翅片和规则翅片的混合物。 形成一个鳍片的半导体制造工艺包括形成一个鳍片的光刻开口，可选地掺杂鳍片的一部分，以及蚀刻鳍片的一部分。
-
公开(公告)号：US20130119482A1
公开(公告)日：2013-05-16
申请号：US13293732
申请日：2011-11-10
IPC分类号： H01L27/088 , H01L21/28
CPC分类号： H01L29/66818 , H01L21/2236 , H01L21/823431 , H01L21/823462 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823857 , H01L21/823878 , H01L21/845 , H01L27/0924 , H01L27/1211
摘要： The disclosure relates to a Fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a top surface; a first fin and a second fin extending above the substrate top surface, wherein each of the fins has a top surface and sidewalls; an insulation layer between the first and second fins extending part way up the fins from the substrate top surface; a first gate dielectric covering the top surface and sidewalls of the first fin having a first thickness and a second gate dielectric covering the top surface and sidewalls of the second fin having a second thickness less than the first thickness; and a conductive gate strip traversing over both the first gate dielectric and second gate dielectric.
摘要翻译： 本发明涉及Fin场效应晶体管（FinFET）。 FinFET的示例性结构包括：包括顶表面的衬底; 在所述基板顶表面上方延伸的第一翅片和第二翅片，其中每个翼片具有顶表面和侧壁; 所述第一和第二翅片之间的绝缘层从所述基板顶表面向上延伸所述翅片; 覆盖第一鳍片的顶表面和第一鳍片的侧壁的第一栅极电介质和覆盖第二鳍片的顶表面和第二鳍片的侧壁的第二栅极电介质具有小于第一厚度的第二厚度; 以及穿过第一栅极电介质和第二栅极电介质两端的导电栅极条。
-
公开(公告)号：US20120273899A1
公开(公告)日：2012-11-01
申请号：US13416862
申请日：2012-03-09
申请人： Clement Hsingjen WANN , Chih-Sheng CHANG , Yi-Tang LIN , Ming-Feng SHIEH , Ting-Chu KO , Chung-Hsien CHEN
发明人： Clement Hsingjen WANN , Chih-Sheng CHANG , Yi-Tang LIN , Ming-Feng SHIEH , Ting-Chu KO , Chung-Hsien CHEN
IPC分类号： H01L27/088 , G03F1/00 , G06F17/50
CPC分类号： H01L27/0886 , G03F1/00 , G06F17/5068 , G06F17/5081 , H01L21/823821 , H01L21/845 , H01L23/48 , H01L27/0207 , H01L29/41791 , H01L29/66795 , H01L29/7831 , H01L2924/0002 , H01L2924/00
摘要： A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.
摘要翻译： 公开了一种用于从具有平面晶体管的器件的第一布局生成具有FinFET的器件的布局的方法。 分析平面布局，并以相符的方式生成相应的FinFET结构。 然后优化所得的FinFET结构。 在验证并输出FinFET布局之前，可能会产生虚拟图案和新的金属层。
-
公开(公告)号：US20120278781A1
公开(公告)日：2012-11-01
申请号：US13416907
申请日：2012-03-09
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.
-
公开(公告)号：US20120278777A1
公开(公告)日：2012-11-01
申请号：US13416742
申请日：2012-03-09
申请人： Yi-Tang LIN , Cheok-Kei LEI , Shu-Yu CHEN , Yu-Ning CHANG , Hsiao-Hui CHEN , Chih-Sheng CHANG , Chien-Wen CHEN , Clement Hsingjen WANN
发明人： Yi-Tang LIN , Cheok-Kei LEI , Shu-Yu CHEN , Yu-Ning CHANG , Hsiao-Hui CHEN , Chih-Sheng CHANG , Chien-Wen CHEN , Clement Hsingjen WANN
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5068 , H01L21/823821 , H01L27/0207
摘要： A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.
-
公开(公告)号：US20120278776A1
公开(公告)日：2012-11-01
申请号：US13416642
申请日：2012-03-09
申请人： Cheok-Kei LEI , Yi-Tang LIN , Hsiao-Hui CHEN , Yu-Ning CHANG , Shu-Yu CHEN , Chien-Wen CHEN , Chih-Sheng CHANG , Clement Hsingjen WANN
发明人： Cheok-Kei LEI , Yi-Tang LIN , Hsiao-Hui CHEN , Yu-Ning CHANG , Shu-Yu CHEN , Chien-Wen CHEN , Chih-Sheng CHANG , Clement Hsingjen WANN
IPC分类号： G06F17/50
CPC分类号： H01L27/0207 , G06F17/5068 , H01L21/823821
摘要： A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated.
摘要翻译： 公开了一种用于从具有平面晶体管的器件的第一布局生成具有FinFET的器件的布局的方法。 分析平面布局并生成相应的FinFET结构。
-
公开(公告)号：US20120306002A1
公开(公告)日：2012-12-06
申请号：US13585436
申请日：2012-08-14
IPC分类号： H01L29/78 , H01L27/088 , H01L21/336
CPC分类号： H01L29/7851 , H01L21/823431 , H01L29/165 , H01L29/267 , H01L29/66795 , H01L29/7848 , H01L2029/7857
摘要： This description relates to a fin field-effect-transistor (FinFET) including a substrate and a fin structure on the substrate. The fin structure includes a channel between a source and a drain, wherein the source, the drain, and the channel have a first type dopant, and the channel comprises at least one of a Ge, SiGe, or III-V semiconductor. The FinFET further includes a gate dielectric layer over the channel and a gate over the gate dielectric layer. The FinFET further includes a nitride spacer on the substrate adjacent the gate and an oxide layer between the nitride spacer and the gate and between the nitride spacer and the substrate.
摘要翻译： 本说明书涉及在基板上包括基板和翅片结构的鳍状场效应晶体管（FinFET）。 鳍结构包括源极和漏极之间的沟道，其中源极，漏极和沟道具有第一类型掺杂物，并且沟道包括Ge，SiGe或III-V半导体中的至少一个。 FinFET还包括通道上的栅极介电层和栅极电介质层上的栅极。 FinFET还包括邻近栅极的衬底上的氮化物间隔物和氮化物间隔物和栅极之间以及氮化物间隔物和衬底之间的氧化物层。
-
公开(公告)号：US20110049613A1
公开(公告)日：2011-03-03
申请号：US12757271
申请日：2010-04-09
IPC分类号： H01L29/78 , H01L21/336 , H01L27/088
CPC分类号： H01L29/7851 , H01L21/823431 , H01L29/165 , H01L29/267 , H01L29/66795 , H01L29/7848 , H01L2029/7857
摘要： A FinFET includes a substrate and a fin structure on the substrate. The fin structure includes a channel between a source and a drain, wherein the source, the drain, and the channel have the first type dopant. The channel includes a Ge, SiGe, or III-V semiconductor. A gate dielectric layer is located over the channel and a gate is located over the gate dielectric layer.
摘要翻译： FinFET在衬底上包括衬底和翅片结构。 鳍结构包括源极和漏极之间的沟道，其中源极，漏极和沟道具有第一类型的掺杂剂。 该通道包括Ge，SiGe或III-V半导体。 栅极介电层位于沟道上方，栅极位于栅极介电层上。
-
公开(公告)号：US20130248927A1
公开(公告)日：2013-09-26
申请号：US13428972
申请日：2012-03-23
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66545 , H01L21/02609 , H01L21/28506 , H01L29/165 , H01L29/41791 , H01L29/4966 , H01L29/517 , H01L29/66636 , H01L29/78 , H01L29/7848 , H01L29/785 , H01L2924/0002 , H01L2924/00
摘要： A contact structure for a semiconductor device includes a substrate comprising a major surface and a cavity. A bottom surface of the cavity is lower than the major surface. The contact structure also includes a strained material in the cavity, and a lattice constant of the strained material is different from lattice constant of the substrate. The contact structure also includes a first metal layer over the strained material, a dielectric layer over the first metal layer, and a second metal layer over the dielectric layer. The dielectric layer has a thickness ranging from 1 nm to 10 nm.
摘要翻译： 用于半导体器件的接触结构包括包括主表面和腔的衬底。 空腔的底面低于主表面。 接触结构还包括空腔中的应变材料，并且应变材料的晶格常数不同于衬底的晶格常数。 接触结构还包括应变材料上的第一金属层，第一金属层上的电介质层和介电层上的第二金属层。 电介质层的厚度范围为1nm至10nm。
-
公开(公告)号：US20110079829A1
公开(公告)日：2011-04-07
申请号：US12761686
申请日：2010-04-16
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/785 , H01L29/41791 , H01L29/66795 , H01L2029/7858
摘要： A Fin field effect transistor (FinFET) includes a fin-channel body over a substrate. A gate electrode is disposed over the fin-channel body. At least one source/drain (S/D) region is disposed adjacent to the fin-channel body. The at least one S/D region is substantially free from including any fin structure.
摘要翻译： Fin场效应晶体管（FinFET）包括在衬底上的鳍状沟道体。 栅电极设置在翅片通道体的上方。 至少一个源极/漏极（S / D）区域邻近鳍状物通道本体设置。 所述至少一个S / D区域基本上不包括任何鳍结构。
-
-
-
-
-
-
-
-
-
搜索结果
23 条记录 (耗时 0.034 秒)
