公开(公告)号：US11631609B2

公开(公告)日：2023-04-18

申请号：US17443117

申请日：2021-07-21

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Heimanu Niebojewski ,  François Andrieu ,  Claire Fenouillet-Beranger

IPC分类号： H01L21/762 ,  H01L29/06 ,  H01L29/40 ,  H01L27/13

摘要： A method for manufacturing a microelectronic device from a semiconductor-on-insulator substrate, the device having active components formed in active areas of the substrate separated by isolation trenches and which are delimited by first sidewalls, the isolation trenches being filled, at least partially, with a first dielectric material, includes a step of chemically attacking a passive section of the first bottom of the isolation trenches configured to generate, at said section, a roughness quadratic mean comprised between 2 nm and 6 nm. The method also includes a step of forming a passive component covering the first dielectric material and directly above the passive section.

公开(公告)号：US11646196B2

公开(公告)日：2023-05-09

申请号：US17445747

申请日：2021-08-24

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Heimanu Niebojewski ,  Christophe Plantier ,  Shay Reboh

IPC分类号： H01L21/02 ,  H01L29/165 ,  H01L29/66

CPC分类号： H01L21/02236 ,  H01L21/02532 ,  H01L29/165 ,  H01L29/66553

摘要： Making of a transistor structure comprising in this order:



forming semiconductor blocks made of SixGe1-x over the surface semiconductor layer and on either side of insulating spacers, the semiconductor blocks having lateral facets,
growth of a silicon-based layer over the semiconductor blocks, so as to fill cavities located between said facets and said insulating spacers,
thermal oxidation to perform a germanium enrichment of semiconductor portions of the surface semiconductor layer disposed on either side of the spacers.

公开(公告)号：US20160260819A1

公开(公告)日：2016-09-08

申请号：US15058615

申请日：2016-03-02

申请人： Commissariat A L'Energie Atomique et aux Energies Alternatives

发明人： Julien BORREL ,  Louis Hutin ,  Yves Morand ,  Fabrice Nemouchi ,  Heimanu Niebojewski

IPC分类号： H01L29/66 ,  H01L21/768 ,  H01L29/51 ,  H01L23/535 ,  H01L29/772 ,  H01L29/423

CPC分类号： H01L29/66553 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0895 ,  H01L29/42364 ,  H01L29/512 ,  H01L29/772

摘要： A field-effect transistor, including a source, drain and channel formed in a semiconductor layer a gate stack placed above the channel, including a metal electrode, a first layer of electrical insulator placed between the metal electrode and the channel, and a second layer of electrical insulator covering the metal electrode; a metal contact placed plumb with the source or drain and at least partially plumb with said gate stack; and a third layer of electrical insulator placed between said metal contact and said source or said drain.

摘要翻译： 一种场效应晶体管，包括在半导体层中形成的源极，漏极和沟道，位于沟道上方的栅极堆叠，包括金属电极，放置在金属电极和沟道之间的第一绝缘体层和第二层 覆盖金属电极的电绝缘体; 金属接触件放置铅与源或漏极并且至少部分地与所述栅极叠层相垂直; 以及放置在所述金属触点和所述源极或所述漏极之间的第三层电绝缘体。

公开(公告)号：US09240325B2

公开(公告)日：2016-01-19

申请号：US14498091

申请日：2014-09-26

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (Crolles 2) SAS

发明人： Sébastien Barnola ,  Yves Morand ,  Heimanu Niebojewski

IPC分类号： H01L29/423 ,  H01L29/78 ,  H01L21/283 ,  H01L29/66 ,  H01L21/28 ,  H01L29/49

CPC分类号： H01L29/42372 ,  H01L21/28008 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/283 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/45 ,  H01L29/49 ,  H01L29/4933 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78

摘要： A method includes making a gate stack on the surface of an active zone, including depositing a first dielectric layer; depositing a gate conductive layer; depositing a first metal layer; depositing a second metal layer; depositing a second dielectric layer; partially etching the gate stack for the formation of a gate zone on the active zone; making insulating spacers on either side of the gate zone on the active zone; making source and drain electrodes zones; making silicidation zones on the surface of the source and drain zones; etching, in the gate zone on the active zone, the second dielectric layer and the second metal layer with stopping on the first metal layer, so as to form a cavity between the insulating spacers; making a protective plug at the surface of the first metal layer of the gate zone on the active zone, where the protective plug fills the cavity.

摘要翻译： 一种方法包括在有源区的表面上形成栅极堆叠，包括沉积第一介电层; 沉积栅极导电层; 沉积第一金属层; 沉积第二金属层; 沉积第二电介质层; 部分地蚀刻栅极堆叠以在有源区上形成栅极区; 在活动区域​​上的栅极区域的任一侧上制造绝缘垫片; 制造源极和漏极区域; 在源极和漏极区域的表面上形成硅化物区域; 在活性区域的栅极区域中蚀刻在第一金属层上停止的第二介电层和第二金属层，以在绝缘间隔物之间​​形成空腔; 在活动区域​​上的栅极区域的第一金属层的表面上形成保护塞，其中保护塞填充空腔。

公开(公告)号：US20130295734A1

公开(公告)日：2013-11-07

申请号：US13871884

申请日：2013-04-26

申请人： STMicroelectronics S.A. ,  Commissariat a l'Energie Atomique et aux Energies Alternatives

发明人： Heimanu Niebojewski ,  Yves Morand ,  Cyrille Le Royer ,  Fabrice Nemouchi

IPC分类号： H01L29/66

CPC分类号： H01L29/66477 ,  H01L21/28247 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823443 ,  H01L21/823475 ,  H01L21/84 ,  H01L29/66545 ,  H01L29/66606

摘要： A method for forming gate, source, and drain contacts on a MOS transistor having an insulated gate including polysilicon covered with a metal gate silicide, this gate being surrounded with at least one spacer made of a first insulating material, the method including the steps of a) covering the structure with a second insulating material and leveling the second insulating material to reach the gate silicide; b) oxidizing the gate so that the gate silicide buries and covers the a silicon oxide; c) selectively removing the second insulating material; and d) covering the structure with a first conductive material and leveling the first conductive material all the way to a lower level at the top of the spacer.

摘要翻译： 一种用于在MOS晶体管上形成栅极，源极和漏极接触的方法，其具有包括被金属栅极硅化物覆盖的多晶硅的绝缘栅极，该栅极由至少一个由第一绝缘材料制成的隔离物包围，该方法包括以下步骤： a）用第二绝缘材料覆盖结构并使第二绝缘材料平整以到达栅极硅化物; b）氧化栅极，使得栅极硅化物掩埋并覆盖氧化硅; c）选择性地去除所述第二绝缘材料; 以及d）用第一导电材料覆盖所述结构，并且将所述第一导电材料一直调整到所述隔离物顶部的较低水平。

公开(公告)号：US11387100B2

公开(公告)日：2022-07-12

申请号：US17016634

申请日：2020-09-10

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Heimanu Niebojewski

IPC分类号： H01L21/02 ,  H01L21/306 ,  H01L21/762

摘要： A method for manufacturing a mixed substrate having, on a main face of a support substrate, a first region and a second region, includes a) providing a starting substrate which comprises an intermediate layer, consisting of the second material, and the support substrate; b) forming a mask which comprises an aperture delimiting the first region; c) forming a cavity; and d) forming the first region by epitaxially growing the first material in a single crystal form in the cavity The method includes step c1), performed before step d), of forming a protective layer, made of an amorphous material, overlaying the flank of the cavity and leaving the bottom of said cavity exposed to the external environment.

公开(公告)号：US09831319B2

公开(公告)日：2017-11-28

申请号：US15058615

申请日：2016-03-02

申请人： Commissariat A L'Energie Atomique et aux Energies Alternatives

发明人： Julien Borrel ,  Louis Hutin ,  Yves Morand ,  Fabrice Nemouchi ,  Heimanu Niebojewski

IPC分类号： H01L29/66 ,  H01L29/08 ,  H01L21/768 ,  H01L23/535 ,  H01L29/423 ,  H01L29/51 ,  H01L29/772

CPC分类号： H01L29/66553 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0895 ,  H01L29/42364 ,  H01L29/512 ,  H01L29/772

摘要： A field-effect transistor, including a source, drain and channel formed in a semiconductor layer a gate stack placed above the channel, including a metal electrode, a first layer of electrical insulator placed between the metal electrode and the channel, and a second layer of electrical insulator covering the metal electrode; a metal contact placed plumb with the source or drain and at least partially plumb with said gate stack; and a third layer of electrical insulator placed between said metal contact and said source or said drain.

公开(公告)号：US20150091089A1

公开(公告)日：2015-04-02

申请号：US14499545

申请日：2014-09-29

申请人： STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

发明人： Heimanu Niebojewski ,  Yves Morand ,  Cyrille Le Royer ,  Olivier Rozeau

IPC分类号： H01L29/51 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L29/515 ,  H01L29/0843 ,  H01L29/4983 ,  H01L29/4991 ,  H01L29/51 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/78

摘要： A MOS transistor has a gate insulator layer that is made of a material of high dielectric constant deposited on a substrate. The gate insulator layer extends, with a constant thickness, under and beyond a gate stack. Spacers of low dielectric constant are formed on either side of the gate stack and vertically separated from the substrate by the extension of the gate insulator layer beyond the sides of the gate stack. The spacers of low dielectric constant are preferably air spacers.

摘要翻译： MOS晶体管具有由沉积在衬底上的高介电常数材料制成的栅极绝缘体层。 栅极绝缘体层以恒定的厚度延伸到栅极堆叠之下和之外。 通过栅极绝缘体层的延伸超过栅极叠层的侧面，在栅极叠层的任一侧上形成具有低介电常数的隔板并与衬底垂直分离。 低介电常数的间隔物优选为空气间隔物。