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    MEMORY WITH OUTPUT CONTROL
    1.
    发明申请
    MEMORY WITH OUTPUT CONTROL 审中-公开
    带输出控制的存储器

    公开(公告)号：US20170076789A1

    公开(公告)日：2017-03-16

    申请号：US15345552

    申请日：2016-11-08

    Applicant: Conversant Intellectual Property Management Inc.

    Inventor： HakJune OH ,  Hong Beom PYEON ,  Jin-Ki KIM

    IPC: G11C11/56 ,  G11C16/34 ,  G11C16/26 ,  G11C16/16 ,  G06F1/12 ,  G11C16/10

    CPC classification number: G11C11/5628 ,  G06F1/12 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C2207/107

    Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

    Abstract translation: 公开了一种用于控制向半导体存储器中的串行数据链路接口的输出端口传送数据的装置，系统和方法。 在一个示例中，闪存设备可以具有多个串行数据链路，多个存储器组和控制输入端口，其使得存储器设备能够将串行数据传送到存储器件的串行数据输出端口。 在另一示例中，闪存器件可以具有单个串行数据链路，单个存储体，串行数据输入端口，用于接收输出使能信号的控制输入端口。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。

    MEMORY WITH OUTPUT CONTROL
    2.
    发明申请
    MEMORY WITH OUTPUT CONTROL 审中-公开

    公开(公告)号：US20190214077A1

    公开(公告)日：2019-07-11

    申请号：US16249482

    申请日：2019-01-16

    Applicant: Conversant Intellectual Property Management Inc.

    Inventor： HakJune OH ,  Hong Beom PYEON ,  Jin-Ki KIM

    IPC: G11C11/56 ,  G11C16/34 ,  G11C16/16 ,  G06F1/12 ,  G11C16/26 ,  G11C7/10 ,  G11C16/10

    Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

    SYSTEM HAVING ONE OR MORE MEMORY DEVICES
    5.
    发明申请
    SYSTEM HAVING ONE OR MORE MEMORY DEVICES 审中-公开
    具有一个或多个记忆设备的系统

    公开(公告)号：US20140325178A1

    公开(公告)日：2014-10-30

    申请号：US14331036

    申请日：2014-07-14

    Applicant: Conversant Intellectual Property Management Inc.

    Inventor： Steven PRZYBYLSKI ,  Roland SCHUETZ ,  HakJune OH ,  Hong Beom PYEON

    IPC: G06F3/06

    CPC classification number: G06F3/0629 ,  G06F3/0604 ,  G06F3/0673 ,  G06F13/4243 ,  G06F13/4256 ,  G11C7/10 ,  G11C7/1042 ,  G11C7/20 ,  G11C8/06 ,  G11C8/10 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A system having serially connected memory devices in a ring topology organization to realize high speed performance. The memory devices have dynamically configurable data widths such that the system can operate with up to a maximum common number of active data pads to maximize performance, or to operate with a single active data pad to minimize power consumption. Therefore the system can include a mix of memory devices having different data widths. The memory devices are dynamically configurable through the issuance of a single command propagated serially through all the memory devices from the memory controller in a broadcast operation. Robust operation of the system is ensured by implementing a data output inhibit algorithm, which prevents valid data from being provided to the memory controller when read output control signal is received out of its proper sequence.

    Abstract translation: 一种在环形拓扑组织中具有串联连接的存储器件以实现高速性能的系统。 存储器件具有动态可配置的数据宽度，使得系统可以以高达最大公共数量的有源数据焊盘操作以最大化性能，或者使用单个有源数据焊盘操作以最小化功耗。 因此，系统可以包括具有不同数据宽度的存储器件的混合。 通过在广播操作中通过从存储器控制器的所有存储器装置串行传播的单个命令的发布来动态地配置存储器件。 通过实施数据输出禁止算法来确保系统的稳健运行，当从其正确的序列中接收到读取输出控制信号时，该算法防止有效数据被提供给存储器控制器。

    DYNAMIC RANDOM ACCESS MEMORY WITH FULLY INDEPENDENT PARTIAL ARRAY REFRESH FUNCTION
    6.
    发明申请
    DYNAMIC RANDOM ACCESS MEMORY WITH FULLY INDEPENDENT PARTIAL ARRAY REFRESH FUNCTION 有权
    具有完全独立部分阵列刷新功能的动态随机访问记忆

    公开(公告)号：US20140233325A1

    公开(公告)日：2014-08-21

    申请号：US14265852

    申请日：2014-04-30

    Applicant: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

    Inventor： Jin-Ki KIM ,  HakJune OH

    IPC: G11C11/406

    CPC classification number: G11C11/40615 ,  G11C11/406 ,  G11C11/40607 ,  G11C11/40618 ,  G11C11/40622

    Abstract: A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing. The PASR settings are made by a memory controller. Any kind of combinations of subblock addresses may be selected. Thus, the memory subblocks are fully independently refreshed. User selectable memory arrays for data retention provide effective memory control programming especially for low power mobile application.

    Abstract translation: 动态随机存取存储器件包括多个存储器子块。 每个子块具有连接多个数据存储单元的多个字线。 部分阵列自刷新（PASR）配置设置是独立制作的。 根据PASR设置，内存子块被寻址以进行刷新。 PASR设置由内存控制器进行。 可以选择子块地址的任何种类的组合。 因此，存储器子块被完全独立地刷新。 用于数据保留的用户可选择的存储器阵列提供有效的存储器控​​制编程，特别是对于低功率

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