中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

29 records (took 0.018 seconds)

    FLASH MEMORY SYSTEM
    1.
    发明申请
    FLASH MEMORY SYSTEM 审中-公开

    公开(公告)号：US20190303004A1

    公开(公告)日：2019-10-03

    申请号：US16387875

    申请日：2019-04-18

    Applicant: Conversant Intellectual Property Management Inc.

    Inventor： Jin-Ki KIM

    IPC: G06F3/06 ,  G06F12/02

    Abstract: A method and system for controlling an MBC configured flash memory device to store data in an SBC storage mode, or a partial MBC storage mode. In a full MBC storage mode, pages of data are programmed sequentially from a first page to an Nth page for each physical row of memory cells. Up to N virtual page addresses per row of memory cells accompany each page to be programmed for designating the virtual position of the page in the row. For SBC or partial MBC data storage, a flash memory controller issues program command(s) to the MBC memory device using less than the maximum N virtual page addresses for each row. The MBC memory device sequentially executes programming operations up to the last received virtual page address for the row.

    NAND FLASH MEMORY HAVING MULTIPLE CELL SUBSTRATES
    3.
    发明申请
    NAND FLASH MEMORY HAVING MULTIPLE CELL SUBSTRATES 审中-公开

    公开(公告)号：US20170229188A1

    公开(公告)日：2017-08-10

    申请号：US15411138

    申请日：2017-01-20

    Applicant: Conversant Intellectual Property Management Inc.

    Inventor： Jin-Ki KIM

    IPC: G11C16/34 ,  G11C16/16 ,  G11C16/26 ,  G11C16/04

    CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/26 ,  H01L27/11521 ,  H01L27/11524

    Abstract: A NAND flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where NAND cell strings connected to the same bitline are formed in at least two well sectors. At least one well sector can be selectively coupled to an erase voltage during an erase operation, such that unselected well sectors are inhibited from receiving the erase voltage. When the area of the well sectors decrease, a corresponding decrease in the capacitance of each well sector results. Accordingly, higher speed erasing of the NAND flash memory cells relative to a single well memory bank is obtained when the charge pump circuit drive capacity remains unchanged. Alternately, a constant erase speed corresponding to a single well memory bank is obtained by matching a well segment having a specific area to a charge pump with reduced drive capacity. A reduced drive capacity charge pump will occupy less semiconductor chip area, thereby reducing cost.

    NON-VOLATILE MEMORY SERIAL CORE ARCHITECTURE
    5.
    发明申请
    NON-VOLATILE MEMORY SERIAL CORE ARCHITECTURE 审中-公开
    非易失性存储器串行核心架构

    公开(公告)号：US20150049550A1

    公开(公告)日：2015-02-19

    申请号：US14531432

    申请日：2014-11-03

    Applicant: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

    Inventor： Jin-Ki KIM

    IPC: G11C16/04

    CPC classification number: G06F3/061 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0679 ,  G11C5/025 ,  G11C7/1006 ,  G11C7/1033 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/12 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32 ,  G11C2207/107 ,  G11C2216/14 ,  G11C2216/20 ,  G11C2216/30

    Abstract: A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. The memory bank is divided into two halves, where each half is divided into upper and lower sectors. Each sector provides data in parallel to a shared two-dimensional page buffer with an integrated self column decoding circuit. A serial to parallel data converter within the memory bank couples the parallel data from either half to the serial data path core. The shared two-dimensional page buffer with the integrated self column decoding circuit minimizes circuit and chip area overhead for each bank, and the serial data path core reduces chip area typically used for routing wide data buses. Therefore a multiple memory bank system is implemented without a significant corresponding chip area increase when compared to a single memory bank system having the same density.

    Abstract translation: 一种具有串行数据接口和串行数据路径核心的存储器系统，用于从至少一个存储器组接收数据并将数据作为串行比特流提供给至少一个存储体。 记忆库分为两半，每半部分分为上下扇区。 每个扇区使用集成的自列解码电路并行提供与共享的二维页面缓冲器的数据。 存储器中的串行到并行数据转换器将并行数据从一半耦合到串行数据路径核心。 具有集成自列解码电路的共享二维页面缓冲器使每个存储体的电路和芯片面积开销最小化，并且串行数据路径核心减少了通常用于布线宽数据总线的芯片面积。 因此，与具有相同密度的单个存储体系统相比，实现多存储体系统而没有显着相应的芯片面积增加。

    MEMORY WITH OUTPUT CONTROL
    7.
    发明申请
    MEMORY WITH OUTPUT CONTROL 审中-公开
    带输出控制的存储器

    公开(公告)号：US20170076789A1

    公开(公告)日：2017-03-16

    申请号：US15345552

    申请日：2016-11-08

    Applicant: Conversant Intellectual Property Management Inc.

    Inventor： HakJune OH ,  Hong Beom PYEON ,  Jin-Ki KIM

    IPC: G11C11/56 ,  G11C16/34 ,  G11C16/26 ,  G11C16/16 ,  G06F1/12 ,  G11C16/10

    CPC classification number: G11C11/5628 ,  G06F1/12 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C2207/107

    Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

    Abstract translation: 公开了一种用于控制向半导体存储器中的串行数据链路接口的输出端口传送数据的装置，系统和方法。 在一个示例中，闪存设备可以具有多个串行数据链路，多个存储器组和控制输入端口，其使得存储器设备能够将串行数据传送到存储器件的串行数据输出端口。 在另一示例中，闪存器件可以具有单个串行数据链路，单个存储体，串行数据输入端口，用于接收输出使能信号的控制输入端口。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。

    COMPOSITE SEMICONDUCTOR MEMORY DEVICE WITH ERROR CORRECTION
    8.
    发明申请
    COMPOSITE SEMICONDUCTOR MEMORY DEVICE WITH ERROR CORRECTION 审中-公开
    具有错误校正的复合半导体存储器件

    公开(公告)号：US20150309867A1

    公开(公告)日：2015-10-29

    申请号：US14795114

    申请日：2015-07-09

    Applicant: Conversant Intellectual Property Management Inc.

    Inventor： Jin-Ki KIM

    IPC: G06F11/10 ,  H03M13/00 ,  H03M13/05

    CPC classification number: G06F11/1044 ,  G06F11/1048 ,  G11C2029/0411 ,  H03M13/05 ,  H03M13/611

    Abstract: A composite semiconductor memory device, comprising: a plurality of nonvolatile memory devices; and an interface device connected to the plurality of nonvolatile memory devices and for connection to a memory controller, the interface device comprising an error correction coding (ECC) engine. Also, a memory system, comprising: a memory controller; and at least one composite semiconductor memory device configured for being written to and read from by the memory controller and comprising a built-in error correction coding (ECC) engine. Also, a memory system, comprising: a composite semiconductor memory device comprising a plurality of nonvolatile memory devices; and a memory controller connected to the at least one composite semiconductor memory device, for issuing read and write commands to the composite semiconductor memory device to cause data to be written to or read from individual ones of the nonvolatile memory devices; the composite semiconductor memory device providing error-free writing and reading of the data.

    Abstract translation: 一种复合半导体存储器件，包括：多个非易失性存储器件; 以及连接到所述多个非易失性存储器件并且用于连接到存储器控制器的接口设备，所述接口设备包括纠错编码（ECC）引擎。 另外，一种存储器系统，包括：存储器控制器; 以及至少一个复合半导体存储器件，被配置为被存储器控制器写入和读出，并且包括内置纠错编码（ECC）引擎。 另外，一种存储系统，包括：复合半导体存储器件，其包括多个非易失性存储器件; 以及存储器控制器，连接到所述至少一个复合半导体存储器件，用于向所述复合半导体存储器件发出读取和写入命令，以使数据被写入或从所述非易失性存储器件中的各个写入; 所述复合半导体存储器件提供无错误的写入和读取数据。

    BRIDGE DEVICE ARCHITECTURE FOR CONNECTING DISCRETE MEMORY DEVICES TO A SYSTEM
    9.
    发明申请
    BRIDGE DEVICE ARCHITECTURE FOR CONNECTING DISCRETE MEMORY DEVICES TO A SYSTEM 有权
    用于将分离存储器件连接到系统的桥接器件结构

    公开(公告)号：US20140241080A1

    公开(公告)日：2014-08-28

    申请号：US14268350

    申请日：2014-05-02

    Applicant: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

    Inventor： Jin-Ki KIM

    IPC: G11C7/00

    CPC classification number: G11C7/00 ,  G11C5/02 ,  G11C5/025

    Abstract: A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices in response to global memory control signals having a format or protocol that is incompatible with the memory devices. The discrete memory devices can be commercial off-the-shelf memory devices or custom memory devices which respond to native, or local memory control signals. The global and local memory control signals include commands and command signals each having different formats. The composite memory device includes a system in package including the semiconductor dies of the discrete memory devices and the bridge device, or can include a printed circuit board having packaged discrete memory devices and a packaged bridge device mounted thereto.

    Abstract translation: 一种复合存储器件，包括分立存储器件和用于响应具有与存储器件不兼容的格式或协议的全局存储器控制信号来控制分立存储器件的桥接器件。 分立存储器件可以是对现有或本地存储器控制信号进行响应的商业现成存储器件或定制存储器件。 全局和本地存储器控制信号包括各自具有不同格式的命令和命令信号。 复合存储器件包括包括分立存储器件和桥接器件的半导体管芯的封装的系统，或者可以包括具有封装的分立存储器件的印刷电路板和安装在其上的封装桥接器件。

    MEMORY WITH OUTPUT CONTROL
    10.
    发明申请
    MEMORY WITH OUTPUT CONTROL 审中-公开

    公开(公告)号：US20190214077A1

    公开(公告)日：2019-07-11

    申请号：US16249482

    申请日：2019-01-16

    Applicant: Conversant Intellectual Property Management Inc.

    Inventor： HakJune OH ,  Hong Beom PYEON ,  Jin-Ki KIM

    IPC: G11C11/56 ,  G11C16/34 ,  G11C16/16 ,  G06F1/12 ,  G11C16/26 ,  G11C7/10 ,  G11C16/10

    Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

Patent Agency Ranking