公开(公告)号：US09515011B2

公开(公告)日：2016-12-06

申请号：US14289334

申请日：2014-05-28

Applicant: Cree, Inc.

Inventor： Simon Wood ,  James W. Milligan ,  Chris Hermanson

IPC: H01L23/34 ,  H01L23/495 ,  H01L23/29 ,  H01L23/31 ,  H01L23/433 ,  H01L23/66

CPC classification number: H01L23/49562 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/66 ,  H01L2223/6655 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/181 ,  H03F1/565 ,  H03F3/195 ,  H03F3/211 ,  H03F2200/222 ,  H03F2200/225 ,  H03F2200/387 ,  H03F2200/391 ,  H03F2200/451 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A transistor package includes a lead frame, a wide band-gap transistor attached to the lead frame, and an over-mold surrounding the lead frame and the wide band-gap transistor. The wide band-gap transistor has a peak output power greater than 150 W when operated at a frequency up to 3.8 GHz. Using an over-mold along with a wide band-gap transistor in the transistor package allows the transistor package to achieve an exceptionally high efficiency, gain, and bandwidth, while keeping the manufacturing cost of the transistor package low.

Abstract translation: 晶体管封装包括引线框架，附接到引线框架的宽带隙晶体管和围绕引线框架和宽带隙晶体管的覆盖模块。 宽带隙晶体管的工作频率高达3.8 GHz时，峰值输出功率大于150 W。 与晶体管封装中的宽带隙晶体管一起使用模具可以使晶体管封装实现极高的效率，增益和带宽，同时保持晶体管封装的制造成本。

公开(公告)号：US09472480B2

公开(公告)日：2016-10-18

申请号：US14289216

申请日：2014-05-28

Applicant: Cree, Inc.

Inventor： Simon Wood ,  Chris Hermanson

IPC: H01L29/15 ,  H01L31/0256 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/29 ,  H01L23/31 ,  H01L29/20 ,  H01L29/78 ,  H01L23/495 ,  H01L23/00

CPC classification number: H01L23/293 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L29/2003 ,  H01L29/78 ,  H01L2223/6655 ,  H01L2223/6677 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A transistor package includes a lead frame and a gallium nitride (GaN) transistor attached to the lead frame. The lead frame and the GaN transistor are surrounded by an over-mold with a glass transition temperature greater than about 135° C. and a flexural modulus less than about 20 GPa. Using an over-mold with a glass transition temperature greater than about 135° C. and a flexural modulus less than about 20 GPa allows the over-mold to handle the heat produced by the GaN transistor while preventing damage to the GaN transistor due to thermal expansion and/or contraction of the over-mold.

Abstract translation: 晶体管封装包括引线框和附接到引线框的氮化镓（GaN）晶体管。 引线框架和GaN晶体管被玻璃化转变温度大于约135℃并具有小于约20GPa的弯曲模量的外模包围。 使用具有大于约135℃的玻璃化转变温度和小于约20GPa的弯曲模量的过模具允许过模具处理由GaN晶体管产生的热量，同时防止由于热量而损坏GaN晶体管 膨胀和/或收缩的模具。

公开(公告)号：US09407214B2

公开(公告)日：2016-08-02

申请号：US13930544

申请日：2013-06-28

Applicant: Cree, Inc.

Inventor： William Pribble ,  James Milligan ,  Simon Wood

IPC: H03F3/21 ,  H03F3/195 ,  H03F1/56 ,  H03F1/02 ,  H03F3/24

CPC classification number: H03F3/195 ,  H03F1/0288 ,  H03F1/56 ,  H03F3/245 ,  H03F2200/387 ,  H03H7/383

Abstract: A microwave integrated circuit includes a substrate and a power amplifier on the substrate. The power amplifier includes a power divider circuit having an input configured to receive an input RF signal, a base amplifier having an input coupled to a first output of the power divider circuit and a peaking amplifier having an input coupled to a second output of the power divider circuit and an output coupled to an output combining node. The power amplifier further includes an impedance inverter circuit coupling the output of the base amplifier to the output combining node and a load matching circuit having an input coupled to the output combining node and an output configured to be coupled to a load.

Abstract translation: 微波集成电路在衬底上包括衬底和功率放大器。 功率放大器包括功率分配器电路，其具有被配置为接收输入RF信号的输入，具有耦合到功率分配器电路的第一输出的输入的基极放大器和具有耦合到功率的第二输出的输入的峰化放大器 分频器电路和耦合到输出组合节点的输出。 功率放大器还包括将基极放大器的输出耦合到输出组合节点的阻抗反相器电路和具有耦合到输出组合节点的输入的负载匹配电路和被配置为耦合到负载的输出。

公开(公告)号：US20170271497A1

公开(公告)日：2017-09-21

申请号：US15587830

申请日：2017-05-05

Applicant: Cree, Inc.

Inventor： Khaled Fayed ,  Simon Wood

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/205 ,  H01L23/528 ,  H01L29/06 ,  H01L29/20 ,  H01L29/417 ,  H01L23/522

CPC classification number: H01L29/7787 ,  H01L23/5228 ,  H01L23/5286 ,  H01L29/0696 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/42316 ,  H01L29/7786

Abstract: A transistor includes a plurality of gate fingers that extend in a first direction and are spaced apart from each other in a second direction, each of the gate fingers comprising at least spaced-apart and generally collinear first and second gate finger segments that are electrically connected to each other. The first gate finger segments are separated from the second gate finger segments in the first direction by a gap region that extends in the second direction. A resistor is disposed in the gap region.

公开(公告)号：US09641163B2

公开(公告)日：2017-05-02

申请号：US14289080

申请日：2014-05-28

Applicant: Cree, Inc.

Inventor： Mitchell Flowers ,  Simon Wood ,  James W. Milligan

IPC: H01L27/06 ,  H03K5/125 ,  H01L23/495 ,  H03F3/21 ,  H01L23/433 ,  H03F1/56 ,  H03F3/195 ,  H01L23/66 ,  H01L23/31

CPC classification number: H03K5/125 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49513 ,  H01L23/49562 ,  H01L23/66 ,  H01L2223/6655 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/181 ,  H03F1/565 ,  H03F3/195 ,  H03F3/211 ,  H03F2200/451 ,  H03F2203/21103 ,  H03F2203/21106 ,  H03F2203/21139 ,  H03F2203/21142 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A transistor package includes a transistor and one or more bandwidth limiting matching networks. The one or more bandwidth limiting matching networks are coupled to one of a control contact and an output contact of the transistor in order to limit the gain response of the transistor outside of a predetermined frequency band. Specifically, the transistor package has a gain roll-off greater than 0.5 dB within 200 MHz of the predetermined frequency band, while providing signal losses less than 1.0 dB inside the predetermined frequency band at a power level greater than 240 W. By providing the bandwidth limiting matching networks in the transistor package, the gain response of the transistor may be appropriately limited in order to comply with the spectral masking requirements of one or more wireless communications standards, for example, Long Term Evolution (LTE) standards.

公开(公告)号：US09565642B2

公开(公告)日：2017-02-07

申请号：US14251112

申请日：2014-04-11

Applicant: Cree, Inc.

Inventor： William Pribble ,  Simon Wood ,  James W. Milligan

IPC: H01Q11/12 ,  H04B1/04 ,  H04W52/24 ,  H04B1/3805 ,  H04B17/10

CPC classification number: H04W52/241 ,  H04B1/0458 ,  H04B1/3805 ,  H04B17/102 ,  H04B2001/0416

Abstract: A gallium nitride (GaN) radio frequency integrated circuit (RFIC) is configured to receive and amplify a low-level WiFi signal to generate a WiFi transmit signal. By using a GaN RFIC, the performance of the RFIC is significantly improved when compared to conventional RFICs for WiFi signals. In one exemplary embodiment, the RFIC has an error vector magnitude less than 29 dBc, an average power output around 29 dBm, and an average power added efficiency of greater than 25%. In additional embodiments, the RFIC has a gain greater than about 32 dB and a peak output power around −37 dB.

Abstract translation: 氮化镓（GaN）射频集成电路（RFIC）被配置为接收和放大低级WiFi信号以产生WiFi传输信号。 通过使用GaN RFIC，与用于WiFi信号的常规RFIC相比，RFIC的性能显着提高。 在一个示例性实施例中，RFIC具有小于29dBc的误差矢量幅度，大约29dBm的平均功率输出和大于25％的平均功率附加效率。 在另外的实施例中，RFIC具有大于约32dB的增益和约-37dB的峰值输出功率。

公开(公告)号：US20150348885A1

公开(公告)日：2015-12-03

申请号：US14289216

申请日：2014-05-28

Applicant: Cree, Inc.

Inventor： Simon Wood ,  Chris Hermanson

IPC: H01L23/495 ,  H01L29/20 ,  H01L29/78 ,  H01L23/31

CPC classification number: H01L23/293 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L29/2003 ,  H01L29/78 ,  H01L2223/6655 ,  H01L2223/6677 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A transistor package includes a lead frame and a gallium nitride (GaN) transistor attached to the lead frame. The lead frame and the GaN transistor are surrounded by an over-mold with a glass transition temperature greater than about 135° C. and a flexural modulus less than about 20 GPa. Using an over-mold with a glass transition temperature greater than about 135° C. and a flexural modulus less than about 20 GPa allows the over-mold to handle the heat produced by the GaN transistor while preventing damage to the GaN transistor due to thermal expansion and/or contraction of the over-mold.

Abstract translation: 晶体管封装包括引线框和附接到引线框的氮化镓（GaN）晶体管。 引线框架和GaN晶体管被玻璃化转变温度大于约135℃并具有小于约20GPa的弯曲模量的外模包围。 使用具有大于约135℃的玻璃化转变温度和小于约20GPa的弯曲模量的过模具允许过模具处理由GaN晶体管产生的热量，同时防止由于热量而损坏GaN晶体管 膨胀和/或收缩的模具。

公开(公告)号：US20150002227A1

公开(公告)日：2015-01-01

申请号：US13930544

申请日：2013-06-28

Applicant: Cree, Inc.

Inventor： William Pribble ,  James Milligan ,  Simon Wood

IPC: H03F3/21 ,  H03F3/195 ,  H03F1/56

CPC classification number: H03F3/195 ,  H03F1/0288 ,  H03F1/56 ,  H03F3/245 ,  H03F2200/387 ,  H03H7/383

Abstract: A microwave integrated circuit includes a substrate and a power amplifier on the substrate. The power amplifier includes a power divider circuit having an input configured to receive an input RF signal, a base amplifier having an input coupled to a first output of the power divider circuit and a peaking amplifier having an input coupled to a second output of the power divider circuit and an output coupled to an output combining node. The power amplifier further includes an impedance inverter circuit coupling the output of the base amplifier to the output combining node and a load matching circuit having an input coupled to the output combining node and an output configured to be coupled to a load.

Abstract translation: 微波集成电路在衬底上包括衬底和功率放大器。 功率放大器包括功率分配器电路，其具有被配置为接收输入RF信号的输入，具有耦合到功率分配器电路的第一输出的输入的基极放大器和具有耦合到功率的第二输出的输入的峰化放大器 分频器电路和耦合到输出组合节点的输出。 功率放大器还包括将基极放大器的输出耦合到输出组合节点的阻抗反相器电路和具有耦合到输出组合节点的输入的负载匹配电路和被配置为耦合到负载的输出。

公开(公告)号：US10268789B1

公开(公告)日：2019-04-23

申请号：US15723286

申请日：2017-10-03

Applicant: Cree, Inc.

Inventor： Mitch Flowers ,  Ulf Andre ,  Khaled Fayed ,  Simon Wood

IPC: H01L29/66 ,  G06F17/50 ,  H01L27/088 ,  H01L23/66 ,  H01L23/00 ,  H01L29/778 ,  H03F3/213 ,  H03F3/195 ,  H03F1/56 ,  H01L27/02

Abstract: A packaged transistor amplifier includes a package having an input lead and an output lead; a transistor stage having a plurality of unit cell transistors that are electrically coupled to the input lead in parallel, each of the unit cell transistors having an output; a first output bond pad that is coupled to a first subset of the outputs of the unit cell transistors by a first feed network; a second output bond pad that is separate from the first output bond pad, the second output bond pad coupled to a second subset of the outputs of the unit cell transistors by a second feed network; a first output bond wire coupled between the first output bond pad and the output lead; and a second output bond wire coupled between the second output bond pad and the output lead. Related design methods are also provided.

公开(公告)号：US20190102498A1

公开(公告)日：2019-04-04

申请号：US15723286

申请日：2017-10-03

Applicant: Cree, Inc.

Inventor： Mitch Flowers ,  Ulf Andre ,  Khaled Fayed ,  Simon Wood

IPC: G06F17/50 ,  H01L27/02 ,  H01L27/088 ,  H01L23/66 ,  H01L23/00 ,  H01L29/778 ,  H03F3/213 ,  H03F3/195 ,  H03F1/56

Abstract: A packaged transistor amplifier includes a package having an input lead and an output lead; a transistor stage having a plurality of unit cell transistors that are electrically coupled to the input lead in parallel, each of the unit cell transistors having an output; a first output bond pad that is coupled to a first subset of the outputs of the unit cell transistors by a first feed network; a second output bond pad that is separate from the first output bond pad, the second output bond pad coupled to a second subset of the outputs of the unit cell transistors by a second feed network; a first output bond wire coupled between the first output bond pad and the output lead; and a second output bond wire coupled between the second output bond pad and the output lead. Related design methods are also provided.