公开(公告)号：US20170345919A1

公开(公告)日：2017-11-30

申请号：US15531015

申请日：2015-12-08

Applicant: DENSO CORPORATION

Inventor： Kazuhiro OYAMA ,  Yasushi HIGUCHI ,  Seigo OOSAWA ,  Masaki MATSUI ,  Youngshin EUM

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L29/778 ,  H01L29/06 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/4236 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/786

Abstract: A semiconductor device includes a lateral switching device having: a substrate; a channel forming layer that has a heterojunction structure made of a GaN layer and an AlGaN layer and is formed with a recessed portion, on the substrate; a gate structure part that includes a gate insulating film and a gate electrode formed in the recessed portion; and a source electrode and a drain electrode on opposite sides of the gate structure part on the channel forming layer. The AlGaN layer includes a first AlGaN layer that has an Al mixed crystal ratio determining a two dimensional electron gas density, and a second AlGaN layer that has an Al mixed crystal ratio smaller than that of the first AlGaN layer to induce negative fixed charge, and is disposed in contact with the gate structure part and spaced from the source electrode and the drain electrode.

公开(公告)号：US20170162391A1

公开(公告)日：2017-06-08

申请号：US15320799

申请日：2015-03-26

Applicant: DENSO CORPORATION

Inventor： Yoshinori TSUCHIYA ,  Hiroyuki TARUMI ,  Shinichi HOSHI ,  Masaki MATSUI ,  Kenji ITOH ,  Tetsuo NARITA ,  Tetsu KACHI

IPC: H01L21/223 ,  H01L29/04 ,  H01L29/423 ,  H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/10

CPC classification number: H01L21/2233 ,  H01L21/20 ,  H01L21/28264 ,  H01L29/045 ,  H01L29/1041 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/786

Abstract: A semiconductor device includes a GaN device provided with: a substrate made of a semi-insulating material or a semiconductor; a channel-forming layer including a GaN layer arranged on the substrate; a gate structure in which a gate-insulating film in contact with the GaN layer is arranged on the channel-forming layer, the gate structure having a gate electrode arranged across the gate-insulating film; and a source electrode and a drain electrode that are arranged on the channel-forming layer and on opposite sides interposing the gate structure. The donor element concentration at the interface between the gate-insulating film and the GaN layer and at the lattice position on the GaN layer side with respect to the interface is set to be less than or equal to 5.0×1017 cm−3.

公开(公告)号：US20170301765A1

公开(公告)日：2017-10-19

申请号：US15514167

申请日：2015-09-14

Applicant: DENSO CORPORATION

Inventor： Yoshinori TSUCHIYA ,  Shinichi HOSHI ,  Masaki MATSUI ,  Kenji ITOH

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L29/49 ,  H01L29/205 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/4236 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/786

Abstract: In a semiconductor device, a gate insulating film is provided with a multi-layer structure including a first insulating film and a second insulating film. The first insulating film is formed of an insulating film containing an element having an oxygen binding force larger than that of an element contained in the second insulating film, and the total charge amount is increased. Specifically, by performing oxygen anneal, it is possible to perform the step of supplying oxygen into an aluminum oxide film and increase the total charge amount. This allows a negative fixed charge density in the gate insulating film in the vicinity of an interface with a GaN layer to be set to a value of not less than 2.5×1011 cm−2 and allows a normally-off element to be reliably provided.

公开(公告)号：US20140273482A1

公开(公告)日：2014-09-18

申请号：US14159055

申请日：2014-01-20

Applicant: DENSO CORPORATION

Inventor： Yoshinori TSUCHIYA ,  Shinichi HOSHI ,  Masaki MATSUI

IPC: H01L21/67 ,  H01L21/3065

CPC classification number: H01L21/67069 ,  H01J37/321 ,  H01J2237/334 ,  H01L21/30621 ,  H01L21/3065 ,  H01L21/31116 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7787

Abstract: A manufacturing method of a semiconductor device including arranging a compound semiconductor above a stage of a chamber, supplying an etching gas into the chamber, and generating a plasma in the chamber is provided. The compound semiconductor includes a group-III element nitride as a main component. A surface of the compound semiconductor is processed by a dry etching. Light is irradiated into the chamber during the generating of the plasma. A dry etching apparatus including a chamber including a stage, on which a compound semiconductor is mounted, and a light source irradiating light into the chamber is provided. The chamber is supplied with an etching gas. A plasma is generated in the chamber. A surface of the compound semiconductor is an object of a dry etching.

Abstract translation: 提供一种半导体器件的制造方法，其包括将化合物半导体放置在室的阶段之上，将蚀刻气体供应到所述室中，以及在所述室中产生等离子体。 化合物半导体包括III族元素氮化物作为主要成分。 化学半导体的表面通过干蚀刻进行处理。 在产生等离子体期间，光被照射到腔室中。 提供了一种干蚀刻装置，其包括具有其上安装有化合物半导体的平台的腔室和将光照射到腔室中的光源。 该室被供应蚀刻气体。 在室内产生等离子体。 化合物半导体的表面是干蚀刻的目的。