公开(公告)号：US20180248026A1

公开(公告)日：2018-08-30

申请号：US15753342

申请日：2016-09-05

Applicant: DENSO CORPORATION

Inventor： Youngshin EUM ,  Kazuhiro OYAMA ,  Yasushi HIGUCHI ,  Yoshinori TSUCHIYA ,  Shinichi HOSHI

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/812 ,  H01L29/06

Abstract: A semiconductor device includes a conductive substrate, a channel forming layer, a first electrode, and a second electrode. The channel forming layer is located above the conductive substrate and includes at least one hetero-junction structure. The hetero-junction structure includes a first GaN-type semiconductor layer providing a drift region and a second GaN-type semiconductor layer having a bandgap energy greater than the first GaN-type semiconductor layer. A total fixed charge quantity of charges in the first GaN-type layer and the second GaN-type layer is from 0.5×1013 to 1.5×1013 cm−2. The charges in the first GaN-type layer and the second GaN-type layer include charges generated by the polarization in the first GaN-type layer. Accordingly, the semiconductor device capable of improving a break-down voltage and decreasing an on-resistance is obtained.

公开(公告)号：US20180219086A1

公开(公告)日：2018-08-02

申请号：US15578403

申请日：2016-06-14

Applicant: DENSO CORPORATION

Inventor： Yasushi HIGUCHI ,  Shinichi HOSHI ,  Kazuhiro OYAMA

IPC: H01L29/778 ,  H01L29/423

CPC classification number: H01L29/7783 ,  H01L29/0843 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/78

Abstract: A nitride semiconductor device includes a horizontal switching device that includes a substrate, a channel forming layer, a source region, a drain region and a gate region. The source region and the drain region are arranged apart from each other in one direction along a plane of the substrate. The gate region is formed of a p-type semiconductor layer and is arranged between the source region and the drain region. The gate region is divided into multiple parts in a perpendicular direction along the plane of the substrate, the perpendicular direction being perpendicular to an arrangement direction in which the source region and the drain region are arranged. Accordingly, on-resistance is decreased while securing high breakdown voltage.

公开(公告)号：US20170162391A1

公开(公告)日：2017-06-08

申请号：US15320799

申请日：2015-03-26

Applicant: DENSO CORPORATION

Inventor： Yoshinori TSUCHIYA ,  Hiroyuki TARUMI ,  Shinichi HOSHI ,  Masaki MATSUI ,  Kenji ITOH ,  Tetsuo NARITA ,  Tetsu KACHI

IPC: H01L21/223 ,  H01L29/04 ,  H01L29/423 ,  H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/10

CPC classification number: H01L21/2233 ,  H01L21/20 ,  H01L21/28264 ,  H01L29/045 ,  H01L29/1041 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/786

Abstract: A semiconductor device includes a GaN device provided with: a substrate made of a semi-insulating material or a semiconductor; a channel-forming layer including a GaN layer arranged on the substrate; a gate structure in which a gate-insulating film in contact with the GaN layer is arranged on the channel-forming layer, the gate structure having a gate electrode arranged across the gate-insulating film; and a source electrode and a drain electrode that are arranged on the channel-forming layer and on opposite sides interposing the gate structure. The donor element concentration at the interface between the gate-insulating film and the GaN layer and at the lattice position on the GaN layer side with respect to the interface is set to be less than or equal to 5.0×1017 cm−3.

公开(公告)号：US20180130873A1

公开(公告)日：2018-05-10

申请号：US15573200

申请日：2016-06-14

Applicant: DENSO CORPORATION

Inventor： Youngshin EUM ,  Kazuhiro OYAMA ,  Yasushi HIGUCHI ,  Shinichi HOSHI

IPC: H01L29/06 ,  H01L29/778 ,  H01L29/78 ,  H01L29/812 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/20

CPC classification number: H01L29/06 ,  H01L29/0615 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/78 ,  H01L29/812

Abstract: In a semiconductor device, an AlGaN layer includes a first AlGaN layer and a second AlGaN layer. The second AlGaN layer is positioned between a gate structure portion and a drain electrode and is divided into multiple parts in an arrangement direction in which the gate structure portion and the drain electrode are arranged. A second Al mixed crystal ratio of the second AlGaN layer is less than a first Al mixed crystal ratio of the first AlGaN layer. Accordingly, the semiconductor device is a normally-off-type device and is capable of restricting a decrease of a breakdown voltage and an increase of an on-resistance.

公开(公告)号：US20170301765A1

公开(公告)日：2017-10-19

申请号：US15514167

申请日：2015-09-14

Applicant: DENSO CORPORATION

Inventor： Yoshinori TSUCHIYA ,  Shinichi HOSHI ,  Masaki MATSUI ,  Kenji ITOH

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L29/49 ,  H01L29/205 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/4236 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/786

Abstract: In a semiconductor device, a gate insulating film is provided with a multi-layer structure including a first insulating film and a second insulating film. The first insulating film is formed of an insulating film containing an element having an oxygen binding force larger than that of an element contained in the second insulating film, and the total charge amount is increased. Specifically, by performing oxygen anneal, it is possible to perform the step of supplying oxygen into an aluminum oxide film and increase the total charge amount. This allows a negative fixed charge density in the gate insulating film in the vicinity of an interface with a GaN layer to be set to a value of not less than 2.5×1011 cm−2 and allows a normally-off element to be reliably provided.

公开(公告)号：US20190123187A1

公开(公告)日：2019-04-25

申请号：US16092492

申请日：2017-04-06

Applicant: DENSO CORPORATION

Inventor： Hiroyuki TARUMI ,  Kazuhiro OYAMA ,  Youngshin EUM ,  Shinichi HOSHI

IPC: H01L29/778 ,  H01L29/78 ,  H01L29/808 ,  H01L29/20 ,  H01L29/205

Abstract: A semiconductor device has a lateral switching device that includes a channel forming layer, a gate structure portion, a source electrode, a drain electrode, a third semiconductor layer, a fourth semiconductor layer, and a junction gate electrode. The gate structure portion has a gate insulating film provided in a recess portion of the channel forming layer and a MOS gate electrode functioning as a gate electrode of a MOS structure provided on the gate insulating film. The source electrode and the junction gate electrode are coupled through an electrode layer provided on an interlayer insulating film covering the MOS gate electrode. An end of the third semiconductor layer facing the drain electrode protrudes toward the drain electrode from an end of the fourth semiconductor layer facing the drain electrode by a distance in a range of 1 μm to 5 μm both inclusive.

公开(公告)号：US20160372587A1

公开(公告)日：2016-12-22

申请号：US15101156

申请日：2014-08-28

Applicant: DENSO CORPORATION

Inventor： Yoshinori TSUCHIYA ,  Shinichi HOSHI ,  Kazuyoshi TOMITA ,  Kenji ITOH ,  Masahito KODAMA ,  Tsutomu UESUGI

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/06 ,  H01L29/417 ,  H01L29/04 ,  H01L29/66

CPC classification number: H01L29/778 ,  H01L23/291 ,  H01L23/3185 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/66462 ,  H01L29/7787

Abstract: A semiconductor device includes a switching device having: a substrate configured by a semi-insulating material or a semiconductor; a channel forming layer on the substrate that is configured by a compound semiconductor mainly having a group III nitride; a gate structure configured by a gate electrode on the channel forming layer with a gate insulating film interposed therebetween; and a source electrode and a drain electrode on the channel forming layer at both sides of the gate structure respectively, a collapse inhibiting layer on the channel forming layer in an element region of the channel forming layer where the switching device is arranged that is configured by an insulating material; and a leakage inhibiting layer on the channel forming layer in an element isolation region of the channel forming layer surrounding the element region that is configured by an insulating material different from that of the collapse inhibiting layer.

Abstract translation: 一种半导体器件包括：开关器件，具有：由半绝缘材料或半导体构成的衬底; 基板上的沟道形成层，其由主要具有III族氮化物的化合物半导体构成; 由沟道形成层上的栅电极构成的栅极结构，其间插入有栅极绝缘膜; 以及源极电极和漏电极，分别位于栅极结构两侧的沟道形成层上，在沟道形成层的沟道形成层的沟道形成层中的崩溃抑制层，其中沟道形成层的布置有开关器件的元件区域由 绝缘材料; 以及在通过与塌陷抑制层的绝缘材料不同的绝缘材料构成的围绕元件区域的沟道形成层的元件隔离区域中的沟道形成层上的泄漏抑制层。

公开(公告)号：US20140273482A1

公开(公告)日：2014-09-18

申请号：US14159055

申请日：2014-01-20

Applicant: DENSO CORPORATION

Inventor： Yoshinori TSUCHIYA ,  Shinichi HOSHI ,  Masaki MATSUI

IPC: H01L21/67 ,  H01L21/3065

CPC classification number: H01L21/67069 ,  H01J37/321 ,  H01J2237/334 ,  H01L21/30621 ,  H01L21/3065 ,  H01L21/31116 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7787

Abstract: A manufacturing method of a semiconductor device including arranging a compound semiconductor above a stage of a chamber, supplying an etching gas into the chamber, and generating a plasma in the chamber is provided. The compound semiconductor includes a group-III element nitride as a main component. A surface of the compound semiconductor is processed by a dry etching. Light is irradiated into the chamber during the generating of the plasma. A dry etching apparatus including a chamber including a stage, on which a compound semiconductor is mounted, and a light source irradiating light into the chamber is provided. The chamber is supplied with an etching gas. A plasma is generated in the chamber. A surface of the compound semiconductor is an object of a dry etching.

Abstract translation: 提供一种半导体器件的制造方法，其包括将化合物半导体放置在室的阶段之上，将蚀刻气体供应到所述室中，以及在所述室中产生等离子体。 化合物半导体包括III族元素氮化物作为主要成分。 化学半导体的表面通过干蚀刻进行处理。 在产生等离子体期间，光被照射到腔室中。 提供了一种干蚀刻装置，其包括具有其上安装有化合物半导体的平台的腔室和将光照射到腔室中的光源。 该室被供应蚀刻气体。 在室内产生等离子体。 化合物半导体的表面是干蚀刻的目的。