公开(公告)号：US10014211B2

公开(公告)日：2018-07-03

申请号：US15684722

申请日：2017-08-23

Applicant: Micron Technology, Inc.

Inventor： David H. Wells

IPC: H01L21/20 ,  H01L21/764 ,  H01L21/02

CPC classification number: H01L21/764 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/2015

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

公开(公告)号：US09786548B2

公开(公告)日：2017-10-10

申请号：US14712219

申请日：2015-05-14

Applicant: Micron Technology, Inc.

Inventor： David H. Wells

IPC: H01L21/336 ,  H01L21/764 ,  H01L21/20 ,  H01L21/02

CPC classification number: H01L21/764 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/2015

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

公开(公告)号：US20160284832A1

公开(公告)日：2016-09-29

申请号：US15174390

申请日：2016-06-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Can Bayram ,  Christopher Peter D'Emic ,  William J. Gallagher ,  Effendi Leobandung ,  Devendra K. Sadana

IPC: H01L29/778 ,  H01L29/205 ,  H01L27/092 ,  H01L29/06 ,  H01L23/535

CPC classification number: H01L29/7787 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02433 ,  H01L21/0254 ,  H01L21/02645 ,  H01L21/2015 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/823807 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/8252 ,  H01L21/8258 ,  H01L21/84 ,  H01L23/535 ,  H01L27/06 ,  H01L27/0617 ,  H01L27/092 ,  H01L27/1207 ,  H01L29/04 ,  H01L29/045 ,  H01L29/06 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7786

Abstract: A method of forming a structure that can be used to integrate Si-based devices, i.e., nFETs and pFETs, with Group III nitride-based devices is provided. The method includes providing a substrate containing an nFET device region, a pFET device region and a Group III nitride device region, wherein the substrate includes a topmost silicon layer and a silicon layer located beneath the topmost silicon layer. Next, a trench is formed within the Group III nitride device region to expose a sub-surface of the silicon layer. The trench is then partially filled with a Group III nitride base material, wherein the Group III nitride material base material has a topmost surface that is coplanar with, or below, a topmost surface of the topmost silicon layer.

公开(公告)号：US09362281B2

公开(公告)日：2016-06-07

申请号：US14749004

申请日：2015-06-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Can Bayram ,  Christopher Peter D'Emic ,  William J. Gallagher ,  Effendi Leobandung ,  Devendra K. Sadana

IPC: H01L27/092 ,  H01L27/06 ,  H01L29/20 ,  H01L29/16 ,  H01L29/778 ,  H01L29/04 ,  H01L29/06 ,  H01L21/8258 ,  H01L21/8252 ,  H01L21/02 ,  H01L21/306 ,  H01L21/31 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/20

CPC classification number: H01L29/7787 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02433 ,  H01L21/0254 ,  H01L21/02645 ,  H01L21/2015 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/823807 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/8252 ,  H01L21/8258 ,  H01L21/84 ,  H01L23/535 ,  H01L27/06 ,  H01L27/0617 ,  H01L27/092 ,  H01L27/1207 ,  H01L29/04 ,  H01L29/045 ,  H01L29/06 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7786

Abstract: A method of forming a structure that can be used to integrate Si-based devices, i.e., nFETs and pFETs, with Group III nitride-based devices is provided. The method includes providing a substrate containing an nFET device region, a pFET device region and a Group III nitride device region, wherein the substrate includes a topmost silicon layer and a silicon layer located beneath the topmost silicon layer. Next, a trench is formed within the Group III nitride device region to expose a sub-surface of the silicon layer. The trench is then partially filled with a Group III nitride base material, wherein the Group III nitride material base material has a topmost surface that is coplanar with, or below, a topmost surface of the topmost silicon layer.

公开(公告)号：US20100171176A1

公开(公告)日：2010-07-08

申请号：US12725797

申请日：2010-03-17

Applicant: David H. Wells

Inventor： David H. Wells

IPC: H01L23/34 ,  H01L29/786 ,  H01L21/336

CPC classification number: H01L21/764 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/2015

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

Abstract translation: 一些实施例包括在半导体结构内形成空隙的方法。 在一些实施例中，空隙可以用作用于分配冷却剂的微结构，用于引导电磁辐射，或用于材料的分离和/或表征。 一些实施例包括其中具有对应于空隙，导管，绝缘结构，半导体结构或导电结构的微结构的结构。

公开(公告)号：US20240087948A1

公开(公告)日：2024-03-14

申请号：US18518271

申请日：2023-11-22

Applicant: Micron Technology, Inc.

Inventor： David H. Wells

IPC: H01L21/764 ,  H01L21/02 ,  H01L21/20

CPC classification number: H01L21/764 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/2015

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

公开(公告)号：US20170372940A1

公开(公告)日：2017-12-28

申请号：US15684080

申请日：2017-08-23

Applicant: Micron Technology, Inc.

Inventor： David H. Wells

IPC: H01L21/764 ,  H01L21/02 ,  H01L21/20

CPC classification number: H01L21/764 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/2015

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

公开(公告)号：US09564526B2

公开(公告)日：2017-02-07

申请号：US15174390

申请日：2016-06-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Can Bayram ,  Christopher Peter D'Emic ,  William J. Gallagher ,  Effendi Leobandung ,  Devendra K. Sadana

IPC: H01L21/20 ,  H01L29/778 ,  H01L29/06 ,  H01L23/535 ,  H01L27/092 ,  H01L29/205 ,  H01L21/8258 ,  H01L21/02

CPC classification number: H01L29/7787 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02433 ,  H01L21/0254 ,  H01L21/02645 ,  H01L21/2015 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/823807 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/8252 ,  H01L21/8258 ,  H01L21/84 ,  H01L23/535 ,  H01L27/06 ,  H01L27/0617 ,  H01L27/092 ,  H01L27/1207 ,  H01L29/04 ,  H01L29/045 ,  H01L29/06 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7786

Abstract: A method of forming a structure that can be used to integrate Si-based devices, i.e., nFETs and pFETs, with Group III nitride-based devices is provided. The method includes providing a substrate containing an nFET device region, a pFET device region and a Group III nitride device region, wherein the substrate includes a topmost silicon layer and a silicon layer located beneath the topmost silicon layer. Next, a trench is formed within the Group III nitride device region to expose a sub-surface of the silicon layer. The trench is then partially filled with a Group III nitride base material, wherein the Group III nitride material base material has a topmost surface that is coplanar with, or below, a topmost surface of the topmost silicon layer.

Abstract translation: 提供了一种形成可用于将Si基器件（即nFET和pFET）与III族氮化物器件集成的结构的方法。 该方法包括提供包含nFET器件区域，pFET器件区域和III族氮化物器件区域的衬底，其中衬底包括位于最顶层硅层下方的最顶层硅层和<111>硅层。 接下来，在III族氮化物器件区域内形成沟槽以暴露<111>硅层的子表面。 然后将沟槽部分地填充有III族氮化物基材，其中III族氮化物材料基材具有与最顶层硅层的最顶表面共平面或最下表面的最顶表面。

公开(公告)号：US20170012108A1

公开(公告)日：2017-01-12

申请号：US15113475

申请日：2015-01-14

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Jun SAKAKIBARA ,  Nozomu AKAGI ,  Shoji MIZUNO ,  Yuichi TAKEUCHI ,  Katsumi SUZUKI

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/02 ,  H01L23/544 ,  H01L29/16 ,  H01L29/10

CPC classification number: H01L29/66068 ,  H01L21/02378 ,  H01L21/0243 ,  H01L21/02529 ,  H01L21/0262 ,  H01L21/02634 ,  H01L21/0465 ,  H01L21/0475 ,  H01L21/0485 ,  H01L21/049 ,  H01L21/2015 ,  H01L21/2033 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/3083 ,  H01L23/544 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/1037 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/401 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66484 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7831 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method for manufacturing a semiconductor device, when a second conductive type impurity layer is formed to provide a deep layer having a second conductive type in a first concavity and to provide a channel layer having the second conductive type on a surface of a drift layer, an epitaxial growth is performed under a growth condition that a contact trench provided by a recess is formed on a surface of a part of the second conductive type impurity layer corresponding to a center position of the first concavity, and a contact region is formed by ion-implanting a second conductive type impurity on a bottom of the contact trench.

Abstract translation: 在制造半导体器件的方法中，当形成第二导电型杂质层以在第一凹部中提供具有第二导电类型的深层并且在漂移层的表面上提供具有第二导电类型的沟道层 在与第一凹部的中心位置对应的第二导电型杂质层的一部分的表面上形成由凹部设置的接触沟槽的生长条件进行外延生长，并且接触区域由 在接触沟槽的底部离子注入第二导电型杂质。

公开(公告)号：US09331076B2

公开(公告)日：2016-05-03

申请号：US14701595

申请日：2015-05-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Can Bayram ,  Christopher Peter D'Emic ,  William J. Gallagher ,  Effendi Leobandung ,  Devendra K. Sadana

IPC: H01L21/8238 ,  H01L27/092 ,  H01L27/06 ,  H01L29/20 ,  H01L29/16 ,  H01L29/778 ,  H01L29/04 ,  H01L29/06 ,  H01L21/8258 ,  H01L21/8252 ,  H01L21/02 ,  H01L21/306 ,  H01L21/31 ,  H01L21/3205 ,  H01L21/768

CPC classification number: H01L29/7787 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02433 ,  H01L21/0254 ,  H01L21/02645 ,  H01L21/2015 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/823807 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/8252 ,  H01L21/8258 ,  H01L21/84 ,  H01L23/535 ,  H01L27/06 ,  H01L27/0617 ,  H01L27/092 ,  H01L27/1207 ,  H01L29/04 ,  H01L29/045 ,  H01L29/06 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7786

Abstract: A method of forming a structure that can be used to integrate Si-based devices, i.e., nFETs and pFETs, with Group III nitride-based devices is provided. The method includes providing a substrate containing an nFET device region, a pFET device region and a Group III nitride device region, wherein the substrate includes a topmost silicon layer and a silicon layer located beneath the topmost silicon layer. Next, a trench is formed within the Group III nitride device region to expose a sub-surface of the silicon layer. The trench is then partially filled with a Group III nitride base material, wherein the Group III nitride material base material has a topmost surface that is coplanar with, or below, a topmost surface of the topmost silicon layer.

Abstract translation: 提供了一种形成可用于将Si基器件（即nFET和pFET）与III族氮化物器件集成的结构的方法。 该方法包括提供包含nFET器件区域，pFET器件区域和III族氮化物器件区域的衬底，其中衬底包括位于最顶层硅层下方的最顶层硅层和<111>硅层。 接下来，在III族氮化物器件区域内形成沟槽以暴露<111>硅层的子表面。 然后将沟槽部分地填充有III族氮化物基材，其中III族氮化物材料基材具有与最顶层硅层的最顶表面共平面或最下表面的最顶表面。