公开(公告)号：US20110117734A1

公开(公告)日：2011-05-19

申请号：US13014548

申请日：2011-01-26

申请人： Da-Yuan Lee ,  Chien-Hao Huang ,  Chi-Chun Chen ,  Kang-Cheng Lin

发明人： Da-Yuan Lee ,  Chien-Hao Huang ,  Chi-Chun Chen ,  Kang-Cheng Lin

IPC分类号： H01L21/28

CPC分类号： H01L29/513 ,  H01L21/823828 ,  H01L29/4966 ,  H01L29/518

摘要： The present disclosure provides a semiconductor device that includes a semiconductor substrate, and a transistor formed in the substrate. The transistor has a gate structure that includes an interfacial layer formed on the substrate, a high-k dielectric layer formed on the interfacial layer, a capping layer formed on the high-k dielectric layer, the capping layer including a silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof, and a polysilicon layer formed on the capping layer.

摘要翻译： 本公开提供了一种半导体器件，其包括半导体衬底和形成在衬底中的晶体管。 晶体管具有栅极结构，该栅极结构包括形成在衬底上的界面层，形成在界面层上的高k电介质层，形成在高k电介质层上的覆盖层，覆盖层包括氧化硅，氮氧化硅 ，氮化硅或其组合，以及形成在覆盖层上的多晶硅层。

公开(公告)号：US20100052076A1

公开(公告)日：2010-03-04

申请号：US12270311

申请日：2008-11-13

申请人： Da-Yuan Lee ,  Chien-Hao Huang ,  Chi-Chun Chen ,  Kang-Cheng Lin

发明人： Da-Yuan Lee ,  Chien-Hao Huang ,  Chi-Chun Chen ,  Kang-Cheng Lin

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/513 ,  H01L21/823828 ,  H01L29/4966 ,  H01L29/518

摘要： The present disclosure provides a semiconductor device that includes a semiconductor substrate, and a transistor formed in the substrate. The transistor has a gate structure that includes an interfacial layer formed on the substrate, a high-k dielectric layer formed on the interfacial layer, a capping layer formed on the high-k dielectric layer, the capping layer including a silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof, and a polysilicon layer formed on the capping layer.

摘要翻译： 本公开提供了一种半导体器件，其包括半导体衬底和形成在衬底中的晶体管。 晶体管具有栅极结构，该栅极结构包括形成在衬底上的界面层，形成在界面层上的高k电介质层，形成在高k电介质层上的覆盖层，覆盖层包括氧化硅，氮氧化硅 ，氮化硅或其组合，以及形成在覆盖层上的多晶硅层。

公开(公告)号：US20140315358A1

公开(公告)日：2014-10-23

申请号：US13866766

申请日：2013-04-19

申请人： Tsung-Yi Huang ,  Chien-Hao Huang

发明人： Tsung-Yi Huang ,  Chien-Hao Huang

IPC分类号： H01L29/66

CPC分类号： H01L29/66893 ,  H01L29/0649 ,  H01L29/0843 ,  H01L29/66901 ,  H01L29/808

摘要： The present invention discloses a manufacturing method of a junction field effect transistor (JFET). The manufacturing method includes: providing a substrate with a first conductive type, forming a channel region with a second conductive type, forming a field region with the first conductive type, forming a gate with the first conductive type, forming a source with the second conductive type, forming a drain with the second conductive type, and forming a lightly doped region with the second conductive type. The channel region is formed by an ion implantation process step, wherein the lightly doped region is formed by masking a predetermined region from accelerated ions of the ion implantation process step, and diffusing impurities with the second conductive type nearby the predetermined region into it with a thermal process step.

摘要翻译： 本发明公开了一种结型场效应晶体管（JFET）的制造方法。 该制造方法包括：提供具有第一导电类型的衬底，形成具有第二导电类型的沟道区，形成具有第一导电类型的场区，形成具有第一导电类型的栅极，形成具有第二导电 形成具有第二导电类型的漏极，以及形成具有第二导电类型的轻掺杂区域。 沟道区域通过离子注入工艺步骤形成，其中通过从离子注入工艺步骤的加速离子掩蔽预定区域并且将具有第二导电类型的杂质附近的预定区域的杂质扩散到其中以通过离子注入工艺步骤 热处理步骤。

公开(公告)号：US08686504B2

公开(公告)日：2014-04-01

申请号：US13555163

申请日：2012-07-22

申请人： Tsung-Yi Huang ,  Chien-Hao Huang

发明人： Tsung-Yi Huang ,  Chien-Hao Huang

IPC分类号： H01L29/66

CPC分类号： H01L29/78 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66689 ,  H01L29/7816

摘要： The present invention discloses a double diffused drain metal oxide semiconductor (DDDMOS) device and a manufacturing method thereof. The DDDMOS device is formed in a substrate, and includes a first well, a gate, a diffusion region, a source, and a drain. A low voltage device is also formed in the substrate, which includes a second well and a lightly doped drain (LDD) region, wherein the first well and the diffusion region are formed by process steps which also form the second well and the LDD region in the low voltage device, respectively.

公开(公告)号：US07994051B2

公开(公告)日：2011-08-09

申请号：US12253741

申请日：2008-10-17

申请人： Cheng-Lung Hung ,  Yong-Tian Hou ,  Keh-Chiang Ku ,  Chien-Hao Huang

发明人： Cheng-Lung Hung ,  Yong-Tian Hou ,  Keh-Chiang Ku ,  Chien-Hao Huang

IPC分类号： H01L21/00

CPC分类号： H01L21/28088 ,  H01L21/265 ,  H01L21/268 ,  H01L21/32155 ,  H01L21/324 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a high-k dielectric layer over a semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a metal layer over the capping layer, forming a semiconductor layer over the metal layer, performing an implantation process on the semiconductor layer, the implantation process using a species including F, and forming a gate structure from the plurality of layers including the high-k dielectric layer, capping layer, metal layer, and semiconductor layer.

摘要翻译： 本公开提供了制造半导体器件的方法。 该方法包括在半导体衬底上形成高k电介质层，在高k电介质层上形成覆盖层，在覆盖层上形成金属层，在金属层上形成半导体层，对金属层进行注入工艺 半导体层，使用包括F的物质的注入工艺，以及从包括高k电介质层，覆盖层，金属层和半导体层的多个层形成栅极结构。

公开(公告)号：US07741709B2

公开(公告)日：2010-06-22

申请号：US12007284

申请日：2008-01-09

申请人： Chien-Hao Huang ,  Wen-Chih Li

发明人： Chien-Hao Huang ,  Wen-Chih Li

IPC分类号： H01L23/552 ,  H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L23/04

CPC分类号： H05K3/403 ,  H05K3/0052 ,  Y10T29/49169

摘要： An embedded type multifunctional integrated structure for integrating protection components and a method for manufacturing the same are disclosed. The present invention utilizes the concept of multi-layer design to integrate more than two passive components on a component structure that is adhered onto a substrate and is applied to a USB terminal in order to protect an electronic device that uses the USB. Hence, the present invention has an OCP function, an OVP function, and an anti-ESD function at the same time. Therefore, the present invention effectively integrates two or more passive components in order to increase functionality. Moreover, the present invention effectively reduces the size of the passive components on a PCB and reduces the number of solder joints.

摘要翻译： 公开了一种用于集成保护部件的嵌入式多功能一体化结构及其制造方法。 本发明利用多层设计的概念，将多于两个的无源部件集成在粘附到基板上的部件结构上，并将其应用于USB端子，以保护使用USB的电子设备。 因此，本发明同时具有OCP功能，OVP功能和抗ESD功能。 因此，为了增加功能，本发明有效地集成了两个或多个无源部件。 此外，本发明有效地减小了PCB上的无源部件的尺寸，并且减少了焊点的数量。

公开(公告)号：US20100105185A1

公开(公告)日：2010-04-29

申请号：US12259028

申请日：2008-10-27

申请人： Keh-Chiang Ku ,  Cheng-Lung Hung ,  Li-Ting Wang ,  Chien-Hao Chen ,  Chien-Hao Huang ,  Wenli Lin ,  Yu-Chang Lin

发明人： Keh-Chiang Ku ,  Cheng-Lung Hung ,  Li-Ting Wang ,  Chien-Hao Chen ,  Chien-Hao Huang ,  Wenli Lin ,  Yu-Chang Lin

IPC分类号： H01L21/336 ,  H01L21/4763

CPC分类号： H01L21/28052 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28506 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer over the semiconductor substrate; forming a gate electrode layer over the gate dielectric layer; doping carbon and nitrogen into the gate electrode layer; and, after the step of doping carbon and nitrogen, patterning the gate dielectric layer and the gate electrode layer to form a gate dielectric and a gate electrode, respectively.

摘要翻译： 一种形成半导体结构的方法包括提供半导体衬底; 在所述半导体衬底上形成栅介电层; 在所述栅极电介质层上形成栅电极层; 将碳和氮掺杂到栅电极层中; 并且在掺杂碳和氮的步骤之后，分别构图栅极电介质层和栅极电极层以形成栅极电介质和栅电极。

公开(公告)号：US20070148823A1

公开(公告)日：2007-06-28

申请号：US11641830

申请日：2006-12-20

申请人： Chien-Hao Huang ,  Wen-Chih Li

发明人： Chien-Hao Huang ,  Wen-Chih Li

IPC分类号： H01L21/00

CPC分类号： H01C7/021 ,  H01C1/1406 ,  H01C17/281

摘要： A method of manufacturing an electronic protection device comprises: providing a substrate mother board with a top surface and a bottom surface; forming a first conductive layer and a second conductive layer on the top surface and the bottom surface, respectively; cutting the substrate mother board into a plurality of strip-shaped substrates; and forming insulating layers on surfaces of each of the strip-shaped substrates that are not covered by the first conductive layer and the second conductive layer.

摘要翻译： 一种制造电子保护装置的方法包括：向母板提供顶表面和底表面; 在顶表面和底表面上分别形成第一导电层和第二导电层; 将基板母板切割成多个条形基板; 以及在未被所述第一导电层和所述第二导电层覆盖的所述条形基板的表面上形成绝缘层。

公开(公告)号：US20150028417A1

公开(公告)日：2015-01-29

申请号：US14483520

申请日：2014-09-11

申请人： Tsung-Yi Huang ,  Chien-Hao Huang

发明人： Tsung-Yi Huang ,  Chien-Hao Huang

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08

CPC分类号： H01L29/0878 ,  H01L21/266 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835

摘要： The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate includes isolation regions defining a device region. The high voltage device includes: a drift region, located in the device region, doped with second conductive type impurities; a gate in the device region and on the surface of the substrate; and a second conductive type source and drain in the device region, at different sides of the gate respectively. From top view, the concentration of the second conductive type impurities of the drift region is distributed substantially periodically along horizontal and vertical directions.

摘要翻译： 本发明公开了一种高压器件及其制造方法。 高压器件形成在第一导电型衬底中，其中衬底包括限定器件区域的隔离区域。 高电压装置包括：位于器件区域中的掺杂有第二导电类型杂质的漂移区; 在器件区域和衬底的表面上的栅极; 以及在栅极的不同侧的器件区域中的第二导电类型源极和漏极。 从俯视图，漂移区域的第二导电型杂质的浓度沿水平方向和垂直方向大致周期性地分布。

公开(公告)号：US08685824B2

公开(公告)日：2014-04-01

申请号：US13529963

申请日：2012-06-21

申请人： Tsung-Yi Huang ,  Chien-Hao Huang

发明人： Tsung-Yi Huang ,  Chien-Hao Huang

IPC分类号： H01L21/336

CPC分类号： H01L29/7817 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： The present invention discloses a hybrid high voltage device and a manufacturing method thereof. The hybrid high voltage device is formed in a first conductive type substrate, and includes at least one lateral double diffused metal oxide semiconductor (LDMOS) device region and at least one vent device region, wherein the LDMOS device region and the vent device region are connected in a width direction and arranged in an alternating order. Besides, corresponding high voltage wells, sources, drains, body regions, and gates of the LDMOS device region and the vent device region are connected to each other respectively.

摘要翻译： 本发明公开了一种混合式高压装置及其制造方法。 混合高压器件形成在第一导电型衬底中，并且包括至少一个横向双扩散金属氧化物半导体（LDMOS）器件区域和至少一个通气器件区域，其中LDMOS器件区域和通气器件区域被连接 在宽度方向上以交替的顺序布置。 此外，LDMOS器件区域和通风装置区域的相应的高压井，源极，漏极，体区和栅极分别彼此连接。