公开(公告)号：US20120154020A1

公开(公告)日：2012-06-21

申请号：US13330970

申请日：2011-12-20

申请人： Dae Woong LEE ,  Yu Gyeong HWANG ,  Jae Hyun SON ,  Tae Min KANG ,  Chul Keun YOON ,  Byoung Do LEE ,  Yu Hwan KIM

发明人： Dae Woong LEE ,  Yu Gyeong HWANG ,  Jae Hyun SON ,  Tae Min KANG ,  Chul Keun YOON ,  Byoung Do LEE ,  Yu Hwan KIM

IPC分类号： G11C5/14

CPC分类号： G11C8/12 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/01322 ,  H01L2924/00012 ,  H01L2924/00

摘要： A stack package having stacked chips includes first voltage dropping units respectively formed in the chips; second voltage dropping units respectively formed in the chips; first signal generation units connected in parallel to a first line formed by connecting the first voltage dropping units in series, respectively formed in the chips, and configured to apply high level signals according to a voltage of the first line; second signal generation units connected in parallel to a second line formed by connecting in series the second voltage dropping units, respectively formed in the chips, and configured to apply high level signals according to a voltage of the second line; and chip selection signal generation units respectively formed in the chips, and configured to combine signals outputted from the first signal generation units and the second signal generation units and generate chip selection signals.

摘要翻译： 具有堆叠芯片的堆叠封装包括分别形成在芯片中的第一降压单元; 分别形成在芯片中的第二降压单元; 第一信号发生单元并联连接到通过分别形成在芯片中的串联连接的第一降压单元形成的第一线，并且被配置为根据第一线的电压施加高电平信号; 第二信号发生单元并联连接到通过串联连接分别形成在芯片中的第二降压单元形成的第二线，并且被配置为根据第二线的电压施加高电平信号; 以及芯片选择信号生成单元，分别形成在芯片中，并且被配置为组合从第一信号生成单元和第二信号生成单元输出的信号，并生成芯片选择信号。

公开(公告)号：US20110121454A1

公开(公告)日：2011-05-26

申请号：US12835053

申请日：2010-07-13

申请人： Tae Min KANG ,  You Kyung HWANG ,  Jae-hyun SON ,  Dae Woong LEE ,  Chul Keun YOON ,  Byoung Do LEE ,  Yu Hwan KIM

发明人： Tae Min KANG ,  You Kyung HWANG ,  Jae-hyun SON ,  Dae Woong LEE ,  Chul Keun YOON ,  Byoung Do LEE ,  Yu Hwan KIM

IPC分类号： H01L23/538 ,  H01L21/60

CPC分类号： H01L25/50 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/85 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A stack semiconductor package includes a first insulation member having engagement projections and a second insulation member formed having engagement grooves into which the engagement projections are to be engaged. First conductive members are disposed in the first insulation member and have portions which are exposed on the engagement projections. Second conductive members are disposed in the second insulation member in such a way as to face the first conductive members and have portions which are exposed in the engagement grooves. A first semiconductor chip is disposed within the first insulation member and is electrically connected to the first conductive members. A second semiconductor chip is disposed in the second insulation member and is electrically connected to the second conductive members.

摘要翻译： 堆叠半导体封装包括具有接合突起的第一绝缘构件和形成有接合突起要与其接合的接合槽的第二绝缘构件。 第一导电构件设置在第一绝缘构件中并且具有暴露在接合突起上的部分。 第二导电构件以与第一导电构件相对的方式设置在第二绝缘构件中，并且具有暴露在接合槽中的部分。 第一半导体芯片设置在第一绝缘构件内并与第一导电构件电连接。 第二半导体芯片设置在第二绝缘构件中并与第二导电构件电连接。

公开(公告)号：US20110254167A1

公开(公告)日：2011-10-20

申请号：US12837879

申请日：2010-07-16

申请人： Tae Min KANG ,  You Kyung HWANG ,  Jae-hyun SON ,  Dae Woong LEE ,  Byoung Do LEE ,  Yu Hwan KIM

发明人： Tae Min KANG ,  You Kyung HWANG ,  Jae-hyun SON ,  Dae Woong LEE ,  Byoung Do LEE ,  Yu Hwan KIM

IPC分类号： H01L25/065 ,  H01L23/538

CPC分类号： H01L23/49816 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/4985 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/3512 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stack package includes a first package having a first semiconductor chip and a first encapsulation member which seals the first semiconductor chip. A second package is stacked on the first package, and includes a second semiconductor chip and a second encapsulation member which seals the second semiconductor chip. Flexible conductors are disposed within the first encapsulation member of the first package in such a way as to electrically connect the first package and the second package.

摘要翻译： 堆叠封装包括具有第一半导体芯片的第一封装和密封第一半导体芯片的第一密封构件。 第二封装堆叠在第一封装上，并且包括密封第二半导体芯片的第二半导体芯片和第二封装构件。 柔性导体以这样的方式设置在第一封装的第一封装构件内，以便电连接第一封装和第二封装。

公开(公告)号：US20130001779A1

公开(公告)日：2013-01-03

申请号：US13611630

申请日：2012-09-12

申请人： Tae Min KANG ,  You Kyung HWANG ,  Jae-hyun SON ,  Dae Woong LEE ,  Byoung Do LEE ,  Yu Hwan KIM

发明人： Tae Min KANG ,  You Kyung HWANG ,  Jae-hyun SON ,  Dae Woong LEE ,  Byoung Do LEE ,  Yu Hwan KIM

IPC分类号： H01L23/488 ,  H01L23/48

CPC分类号： H01L23/49816 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/4985 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/3512 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stack package includes a first package having a first semiconductor chip and a first encapsulation member which seals the first semiconductor chip. A second package is stacked on the first package, and includes a second semiconductor chip and a second encapsulation member which seals the second semiconductor chip. Flexible conductors are disposed within the first encapsulation member of the first package in such a way as to electrically connect the first package and the second package.

摘要翻译： 堆叠封装包括具有第一半导体芯片的第一封装和密封第一半导体芯片的第一密封构件。 第二封装堆叠在第一封装上，并且包括密封第二半导体芯片的第二半导体芯片和第二封装构件。 柔性导体以这样的方式设置在第一封装的第一封装构件内，以便电连接第一封装和第二封装。