Methods of forming an isolation layer and methods of manufacturing semiconductor devices having an isolation layer
    1.
    发明授权
    Methods of forming an isolation layer and methods of manufacturing semiconductor devices having an isolation layer 失效
    形成隔离层的方法和制造具有隔离层的半导体器件的方法

    公开(公告)号:US08524569B2

    公开(公告)日:2013-09-03

    申请号:US13109527

    申请日:2011-05-17

    摘要: In a method of forming an isolation layer, first and second trenches are formed on a substrate. The first and the second trenches have first and second widths, respectively, and the second width is greater than the first width. A second isolation layer pattern partially fills the second trench. A first isolation layer pattern and the third isolation layer pattern are formed. The first isolation layer pattern fills the first trench, and the third isolation layer pattern is formed on the second isolation layer pattern and fills a remaining portion of the second trench.

    摘要翻译: 在形成隔离层的方法中,在衬底上形成第一和第二沟槽。 第一和第二沟槽分别具有第一宽度和第二宽度,第二宽度大于第一宽度。 第二隔离层图案部分地填充第二沟槽。 形成第一隔离层图案和第三隔离层图案。 第一隔离层图案填充第一沟槽,并且第三隔离层图案形成在第二隔离层图案上并且填充第二沟槽的剩余部分。

    Method for Fabricating Semiconductor Device
    2.
    发明申请
    Method for Fabricating Semiconductor Device 审中-公开
    半导体器件制造方法

    公开(公告)号:US20110306208A1

    公开(公告)日:2011-12-15

    申请号:US13157393

    申请日:2011-06-10

    IPC分类号: H01L21/28

    CPC分类号: H01L28/91

    摘要: Methods for forming a mold for a storage electrode in a semiconductor device include forming an interlayer dielectric layer including a contact plug on a substrate. A first mold dielectric layer is formed of a first material on the interlayer dielectric layer. A second mold dielectric layer is formed of a second material on the first mold dielectric layer. The second material has a different etch selectivity than the first material. A first opening is formed that penetrates the first and second mold dielectric layers. The first opening is dry etched to define a second opening having a larger width in the first mold dielectric layer than in the second mold dielectric layer based on the different etch selectivity of the first and second mold dielectric layers to define the mold for the storage electrode.

    摘要翻译: 在半导体器件中形成用于存储电极的模具的方法包括在衬底上形成包括接触插塞的层间介电层。 第一模具电介质层由层间电介质层上的第一材料形成。 第二模具电介质层由第一模具电介质层上的第二材料形成。 第二种材料具有与第一种材料不同的蚀刻选择性。 形成穿过第一和第二模具电介质层的第一开口。 基于第一和第二模具电介质层的不同蚀刻选择性来限定用于存储电极的模具,第一开口被干蚀刻以限定在第一模具电介质层中具有比在第二模具电介质层中更大的宽度的第二开口 。

    METHODS OF FORMING AN ISOLATION LAYER AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES HAVING AN ISOLATION LAYER
    3.
    发明申请
    METHODS OF FORMING AN ISOLATION LAYER AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES HAVING AN ISOLATION LAYER 失效
    形成隔离层的方法和制造具有隔离层的半导体器件的方法

    公开(公告)号:US20110281415A1

    公开(公告)日:2011-11-17

    申请号:US13109527

    申请日:2011-05-17

    IPC分类号: H01L21/31

    摘要: In a method of forming an isolation layer, first and second trenches are formed on a substrate. The first and the second trenches have first and second widths, respectively, and the second width is greater than the first width. A second isolation layer pattern partially fills the second trench. A first isolation layer pattern and the third isolation layer pattern are formed. The first isolation layer pattern fills the first trench, and the third isolation layer pattern is formed on the second isolation layer pattern and fills a remaining portion of the second trench.

    摘要翻译: 在形成隔离层的方法中,在衬底上形成第一和第二沟槽。 第一和第二沟槽分别具有第一宽度和第二宽度,第二宽度大于第一宽度。 第二隔离层图案部分地填充第二沟槽。 形成第一隔离层图案和第三隔离层图案。 第一隔离层图案填充第一沟槽,并且第三隔离层图案形成在第二隔离层图案上并且填充第二沟槽的剩余部分。

    Methods of forming integrated circuit capacitors having sidewall supports and capacitors formed thereby
    5.
    发明授权
    Methods of forming integrated circuit capacitors having sidewall supports and capacitors formed thereby 有权
    形成具有侧壁支撑件的集成电路电容器和由此形成的电容器的方法

    公开(公告)号:US08119476B2

    公开(公告)日:2012-02-21

    申请号:US12906184

    申请日:2010-10-18

    IPC分类号: H01L21/8242

    摘要: In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern.

    摘要翻译: 在形成电容器的方法中,可以在基板上形成包括第一绝缘材料的第一模层图案。 第一模层图案可以具有沟槽。 可以在沟槽中形成包括第二绝缘材料的支撑层。 第二绝缘材料可以具有相对于第一绝缘材料的蚀刻选择性。 可以在第一模层图案和支撑层图案上形成第二模层。 可以通过第二模具层和第一模具层图案形成下部电极。 下电极可以与支撑层图案的侧壁接触。 可以去除第一模层图案和第二模层。 电介质层和上电极可以形成在下电极和支撑层图案上。

    METHODS OF FORMING A CAPACITOR STRUCTURE AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME
    6.
    发明申请
    METHODS OF FORMING A CAPACITOR STRUCTURE AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME 审中-公开
    形成电容器结构的方法和使用其制造半导体器件的方法

    公开(公告)号:US20120064680A1

    公开(公告)日:2012-03-15

    申请号:US13228867

    申请日:2011-09-09

    IPC分类号: H01L21/336 H01G13/06

    CPC分类号: H01G13/06

    摘要: A method of forming a capacitor structure and manufacturing a semiconductor device, the method of forming a capacitor structure including sequentially forming a first mold layer, a supporting layer, a second mold layer, an anti-bowing layer, and a third mold layer on a substrate having a conductive region thereon; partially removing the third mold layer, the anti-bowing layer, the second mold layer, the supporting layer, and the first mold layer to form a first opening exposing the conductive region; forming a lower electrode on a sidewall and bottom of the first opening, the lower electrode being electrically connected to the conductive region; further removing the third mold layer, the anti-bowing layer, and the second mold layer; partially removing the supporting layer to form a supporting layer pattern; removing the first mold layer; and sequentially forming a dielectric layer and upper electrode on the lower electrode and the supporting layer pattern.

    摘要翻译: 一种形成电容器结构并制造半导体器件的方法,形成电容器结构的方法包括:依次形成第一模具层,支撑层,第二模具层,抗弯曲层和第三模具层 衬底,其上具有导电区域; 部分地去除第三模具层,抗弯曲层,第二模具层,支撑层和第一模具层,以形成暴露导电区域的第一开口; 在所述第一开口的侧壁和底部形成下电极,所述下电极电连接到所述导电区域; 进一步去除第三模具层,抗弯曲层和第二模具层; 部分地去除支撑层以形成支撑层图案; 去除第一模具层; 并且在下电极和支撑层图案上依次形成电介质层和上电极。

    Methods of Forming Integrated Circuit Capacitors Having Sidewall Supports and Capacitors Formed Thereby
    8.
    发明申请
    Methods of Forming Integrated Circuit Capacitors Having Sidewall Supports and Capacitors Formed Thereby 有权
    形成具有侧壁支撑和形成电容器的集成电路电容器的方法

    公开(公告)号:US20110159660A1

    公开(公告)日:2011-06-30

    申请号:US12906184

    申请日:2010-10-18

    IPC分类号: H01L21/02 H01G13/00

    摘要: In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern.

    摘要翻译: 在形成电容器的方法中,可以在基板上形成包括第一绝缘材料的第一模层图案。 第一模层图案可以具有沟槽。 可以在沟槽中形成包括第二绝缘材料的支撑层。 第二绝缘材料可以具有相对于第一绝缘材料的蚀刻选择性。 可以在第一模层图案和支撑层图案上形成第二模层。 可以通过第二模具层和第一模具层图案形成下部电极。 下电极可以与支撑层图案的侧壁接触。 可以去除第一模层图案和第二模层。 电介质层和上电极可以形成在下电极和支撑层图案上。

    Integrated circuit capacitors having sidewall supports
    9.
    发明授权
    Integrated circuit capacitors having sidewall supports 有权
    具有侧壁支撑件的集成电路电容器

    公开(公告)号:US08766343B2

    公开(公告)日:2014-07-01

    申请号:US13356032

    申请日:2012-01-23

    IPC分类号: H01L27/108 H01L29/94

    摘要: In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern.

    摘要翻译: 在形成电容器的方法中,可以在基板上形成包括第一绝缘材料的第一模层图案。 第一模层图案可以具有沟槽。 可以在沟槽中形成包括第二绝缘材料的支撑层。 第二绝缘材料可以具有相对于第一绝缘材料的蚀刻选择性。 可以在第一模层图案和支撑层图案上形成第二模层。 可以通过第二模具层和第一模具层图案形成下部电极。 下电极可以与支撑层图案的侧壁接触。 可以去除第一模层图案和第二模层。 电介质层和上电极可以形成在下电极和支撑层图案上。

    INTEGRATED CIRCUIT CAPACITORS HAVING SIDEWALL SUPPORTS
    10.
    发明申请
    INTEGRATED CIRCUIT CAPACITORS HAVING SIDEWALL SUPPORTS 有权
    集成电路电容器具有支持端口

    公开(公告)号:US20120112317A1

    公开(公告)日:2012-05-10

    申请号:US13356032

    申请日:2012-01-23

    IPC分类号: H01L21/02

    摘要: In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern.

    摘要翻译: 在形成电容器的方法中,可以在基板上形成包括第一绝缘材料的第一模层图案。 第一模层图案可以具有沟槽。 可以在沟槽中形成包括第二绝缘材料的支撑层。 第二绝缘材料可以具有相对于第一绝缘材料的蚀刻选择性。 可以在第一模层图案和支撑层图案上形成第二模层。 可以通过第二模具层和第一模具层图案形成下部电极。 下电极可以与支撑层图案的侧壁接触。 可以去除第一模层图案和第二模层。 电介质层和上电极可以形成在下电极和支撑层图案上。