公开(公告)号：US06998870B1

公开(公告)日：2006-02-14

申请号：US10209484

申请日：2002-07-31

申请人： Dale E. Gulick ,  Jonathan P. Dowling

发明人： Dale E. Gulick ,  Jonathan P. Dowling

IPC分类号： H03K17/16

CPC分类号： H04L25/0278 ,  H05K1/0237 ,  H05K1/141 ,  H05K3/222 ,  H05K2201/09727 ,  H05K2201/10325 ,  H05K2201/10734

摘要： A method and apparatus for impedance matching in systems configured for multiple processors is disclosed. In one embodiment, a computer system includes a first processor socket and a second processor socket, each configured to accommodate a processor. The processor sockets may be electrically coupled to each other. A first I/O node may be electrically coupled to the first processor socket and a second I/O node may be electrically coupled to the second processor socket. A processor may be mounted in the first processor socket, while an impedance matching circuit may be mounted in the second processor socket. The impedance matching circuit may electrically couple the processor mounted in the first processor socket to the second I/O node, thereby allowing the computer system to utilize the I/O capability provided by the second I/O node even when a second processor is not present in the system.

摘要翻译： 公开了一种用于多个处理器配置的系统中的阻抗匹配的方法和装置。 在一个实施例中，计算机系统包括第一处理器插座和第二处理器插座，每个被配置为容纳处理器。 处理器插座可以彼此电耦合。 第一I / O节点可以电耦合到第一处理器插槽，并且第二I / O节点可以电耦合到第二处理器插槽。 处理器可以安装在第一处理器插槽中，而阻抗匹配电路可以安装在第二处理器插槽中。 阻抗匹配电路可以将安装在第一处理器插槽中的处理器电耦合到第二I / O节点，从而允许计算机系统利用第二I / O节点提供的I / O能力，即使第二处理器不是 存在于系统中。

公开(公告)号：US07603551B2

公开(公告)日：2009-10-13

申请号：US10419121

申请日：2003-04-18

申请人： Kevin J. McGrath ,  Geoffrey S. Strongin ,  David S. Christie ,  William A. Hughes ,  Dale E. Gulick

发明人： Kevin J. McGrath ,  Geoffrey S. Strongin ,  David S. Christie ,  William A. Hughes ,  Dale E. Gulick

IPC分类号： G06F9/44 ,  H04L29/06

CPC分类号： G06F9/4403

摘要： The initialization of a computer system including a secure execution mode-capable processor includes storing a secure operating system code segment loader to a plurality of locations corresponding to a particular range of addresses within a system memory. The method also includes executing a security initialization instruction. Executing the security initialization instruction may cause several operations to be performed including transmitting a start transaction including a base address of the particular range of addresses. In addition, executing the security instruction may also cause another operation to be performed including retrieving the secure operating system code segment loader from the system memory and transmitting the secure operating system code segment loader for validation as a plurality of data transactions.

摘要翻译： 包括具有安全执行模式能力的处理器的计算机系统的初始化包括将安全操作系统代码段加载器存储到对应于系统存储器内的特定地址范围的多个位置。 该方法还包括执行安全初始化指令。 执行安全初始化指令可能导致执行若干操作，包括发送包括特定地址范围的基地址的开始事务。 此外，执行安全指令还可以引起执行另一操作，包括从系统存储器检索安全操作系统代码段加载器，并将安全操作系统代码段加载器发送为多个数据事务。

公开(公告)号：US07216362B1

公开(公告)日：2007-05-08

申请号：US09853395

申请日：2001-05-11

申请人： Geoffrey S. Strongin ,  Dale E. Gulick

发明人： Geoffrey S. Strongin ,  Dale E. Gulick

IPC分类号： G06F12/14 ,  G06F12/00 ,  G06F7/04 ,  G06F13/00

CPC分类号： G06F12/1441 ,  G06F7/582 ,  G06F12/1458 ,  G06F21/53 ,  G06F21/72

摘要： A method and system for enhanced security and manageability using secure storage. The system may include a crypto-processor and a memory coupled to receive memory transactions through the crypto-processor. The memory transactions are passed to the memory by the crypto-processor. The system may include a first processor, a second processor coupled to the first processor, and a storage device operably coupled to the first processor through the second processor. The second processor is configured to control access to the storage device. The method includes transmitting a request for a memory transaction for a storage location in the storage device and receiving the request for the memory transaction at the crypto-processor. The method also includes determining if the memory transaction is authorized for the storage location, and passing the request for the memory transaction to the storage device if the memory transaction is authorized for the storage location.

摘要翻译： 一种使用安全存储来增强安全性和可管理性的方法和系统。 该系统可以包括加密处理器和耦合以通过密码处理器接收存储器事务的存储器。 存储器事务由加密处理器传递到存储器。 该系统可以包括第一处理器，耦合到第一处理器的第二处理器，以及通过第二处理器可操作地耦合到第一处理器的存储设备。 第二处理器被配置为控制对存储设备的访问。 该方法包括向存储设备发送对存储位置的存储器事务的请求，并在密码处理器处接收对存储器事务的请求。 该方法还包括确定存储器事务是否被授权用于存储位置，并且如果存储器事务被授权用于存储位置，则将存储器事务的请求传递到存储设备。

公开(公告)号：US07210009B2

公开(公告)日：2007-04-24

申请号：US10654734

申请日：2003-09-04

申请人： Dale E. Gulick ,  Geoffrey S. Strongin ,  William A. Hughes

发明人： Dale E. Gulick ,  Geoffrey S. Strongin ,  William A. Hughes

IPC分类号： G06F12/12 ,  G06F12/16

CPC分类号： G06F21/74 ,  G06F21/79 ,  G06F2221/2105 ,  G06F2221/2143

摘要： A computer system includes a processor which may initialize a secure execution mode by executing a security initialization instruction. Further, the processor may operate in the secure execution mode by executing a secure operating system code segment. The computer system also includes a system memory configured to store data in a plurality of locations. The computer system also includes a memory controller which may selectively clear the data from a programmed range of the memory locations of the system memory when enabled in response to a reset of the processor.

摘要翻译： 计算机系统包括可以通过执行安全初始化指令来初始化安全执行模式的处理器。 此外，处理器可以通过执行安全操作系统代码段在安全执行模式下操作。 计算机系统还包括被配置为在多个位置存储数据的系统存储器。 计算机系统还包括存储器控制器，当响应于处理器的复位使能时，存储器控制器可以选择性地从系统存储器的存储器位置的编程范围中清除数据。

公开(公告)号：US07174467B1

公开(公告)日：2007-02-06

申请号：US10185171

申请日：2002-06-28

申请人： Frank P. Helms ,  Dale E. Gulick ,  Larry D. Hewitt ,  William A. Hughes ,  Paul C. Miranda ,  Derrick R. Meyer ,  Scott E. Swanstrom ,  Scott A. White

发明人： Frank P. Helms ,  Dale E. Gulick ,  Larry D. Hewitt ,  William A. Hughes ,  Paul C. Miranda ,  Derrick R. Meyer ,  Scott E. Swanstrom ,  Scott A. White

IPC分类号： G06F1/26 ,  G06F1/28 ,  G06F1/32

CPC分类号： G06F1/324 ,  G06F1/3228 ,  G06F1/3296 ,  G06F9/30083 ,  Y02D10/126 ,  Y02D10/172

摘要： A message based power management approach is utilized to provide power management for a multi-processor system. A power management message is received at one processor of the multi-processor system over an input/output communication link that provides input/output access for the processors of the multi-processor system. The power management message includes a power management field encoding a power management state for processors of the multi-processor system. The processor that received the power management message over the input/output communication link sends a power management message to other processors in the multi-processor system over one or more inter-processor communication links encoding the power management state.

摘要翻译： 利用基于消息的电源管理方法为多处理器系统提供电源管理。 在多处理器系统的一个处理器上通过输入/输出通信链路接收功率管理消息，该输入/输出通信链路为多处理器系统的处理器提供输入/输出接入。 电源管理消息包括对多处理器系统的处理器编码电源管理状态的电源管理字段。 通过输入/输出通信链路接收电力管理消息的处理器通过编码电源管理状态的一个或多个处理器间通信链路向多处理器系统中的其他处理器发送电源管理消息。

公开(公告)号：US07162554B1

公开(公告)日：2007-01-09

申请号：US09904373

申请日：2001-07-11

申请人： Terry Lynn Cole ,  Dale E. Gulick ,  Timothy C. Maleck ,  Frank Barth ,  Joerg Winkler

发明人： Terry Lynn Cole ,  Dale E. Gulick ,  Timothy C. Maleck ,  Frank Barth ,  Joerg Winkler

IPC分类号： G06F13/00 ,  G06F3/00

CPC分类号： G06F13/385

摘要： A method an apparatus for providing capability information to a shared controller. In one embodiment, a peripheral bus host controller may be shared by a plurality of peripheral devices coupled to a peripheral bus. The peripheral devices may include coder/decoder (codec) circuitry, and may be implemented using a riser card. The host controller may be configured to query the bus for peripheral devices by reading each address on the bus. During the querying process, the host controller may detect one or more peripheral devices coupled to the bus. Following the completion of the querying of the bus, the host controller may then begin reading configuration information from each of the detected devices. The host controller may employ one or more of several different techniques in order to read configuration information from the peripheral device. The configuration information at a minimum includes a device identifier, which may identify the vendor and the function of the device. Additional information needed to configure the device to communicate over the peripheral bus may also be obtained with a read of the device, or various lookup mechanisms, such as a lookup table or a tree-like data structure. After configuration information has been obtained for each device coupled to the bus, the host controller may dynamically configure each of the devices for communication over the bus, thereby allowing the flexibility to enumerate riser cards and add new functions through peripheral devices to the computer system in which the bus is implemented.

摘要翻译： 一种用于向共享控制器提供能力信息的装置的方法。 在一个实施例中，外围总线主机控制器可以由耦合到外围总线的多个外围设备共享。 外围设备可以包括编码器/解码器（编解码器）电路，并且可以使用转接卡来实现。 主机控制器可以被配置为通过读取总线上的每个地址来查询外围设备的总线。 在查询过程期间，主机控制器可以检测耦合到总线的一个或多个外围设备。 在完成对总线的查询之后，主机控制器然后可以开始从每个检测到的设备读取配置信息。 主机控制器可以采用几种不同技术中的一种或多种，​​以便从外围设备读取配置信息。 配置信息至少包括设备标识符，其可以标识供应商和设备的功能。 通过设备的读取或诸如查找表或树状数据结构的各种查找机制也可以获得将设备配置成通过外围总线进行通信所需的附加信息。 在针对耦合到总线的每个设备获得配置信息之后，主机控制器可以动态地配置每个设备以通过总线进行通信，从而允许灵活地枚举转接卡并且通过外围设备将新功能添加到计算机系统 总线实施。

公开(公告)号：US07131035B2

公开(公告)日：2006-10-31

申请号：US10283612

申请日：2002-10-30

申请人： Dale E. Gulick ,  Siegfried Kay Hesse

发明人： Dale E. Gulick ,  Siegfried Kay Hesse

IPC分类号： G06F11/00

CPC分类号： G06F11/26

摘要： A diagnosis mechanism for host controllers such as USB (Universal Serial Bus) host controllers is provided. The host controller has a register set that comprises at least one host controller capability register storing data indicative of operational capabilities of the host controller, and at least one host controller operational register storing data for controlling the operation of the host controller. The at least one host controller capability register stores data that is indicative of available diagnostic modes that the host controller can enter. The at least one host controller operational register stores diagnosis data for controlling the operation of the USB host controller in diagnostic modes. This diagnosis mechanism may improve the reliability of the host controller operation.

摘要翻译： 提供了诸如USB（通用串行总线）主机控制器的主机控制器的诊断机制。 主机控制器具有寄存器集合，其包括至少一个主机控制器能力寄存器，其存储指示主机控制器的操作能力的数据，以及存储用于控制主机控制器的操作的数据的至少一个主控制器操作寄存器。 至少一个主机控制器能力寄存器存储指示主机控制器可以进入的可用诊断模式的数据。 所述至少一个主机控制器操作寄存器存储用于以诊断模式控制所述USB主机控制器的操作的诊断数据。 该诊断机制可以提高主机控制器操作的可靠性。

公开(公告)号：US07051218B1

公开(公告)日：2006-05-23

申请号：US10185195

申请日：2002-06-28

申请人： Dale E. Gulick ,  Frank P. Helms ,  Larry D. Hewitt ,  William A. Hughes ,  Paul C. Miranda ,  Derrick R. Meyer ,  Scott E. Swanstrom ,  Scott A. White

发明人： Dale E. Gulick ,  Frank P. Helms ,  Larry D. Hewitt ,  William A. Hughes ,  Paul C. Miranda ,  Derrick R. Meyer ,  Scott E. Swanstrom ,  Scott A. White

IPC分类号： G06F1/30 ,  G06F3/00 ,  G06F13/36

CPC分类号： G06F1/3209 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F1/3296 ,  G06F9/30083 ,  Y02D10/126 ,  Y02D10/151 ,  Y02D10/172

摘要： A message based power management system converts legacy signals used in power management, and other signals used to differentiate between power states, to messages sent over a communication link. A system message sent on a communication link includes a field encoding the level of power management for the device receiving the system message. Further, one or more additional signals, separate from the communication link, may be used to indicate when to take action after the power management message has been received.

摘要翻译： 基于消息的电力管理系统将用于电力管理的传统信号和用于区分电力状态的其他信号转换成通过通信链路发送的消息。 在通信链路上发送的系统消息包括对接收系统消息的设备的电源管理级进行编码的字段。 此外，与通信链路分离的一个或多个附加信号可以用于指示何时在接收到电力管理消息之后采取行动。

公开(公告)号：US07007300B1

公开(公告)日：2006-02-28

申请号：US09870890

申请日：2001-05-30

申请人： Frederick D. Weber ,  Dale E. Gulick ,  Geoffrey S. Strongin

发明人： Frederick D. Weber ,  Dale E. Gulick ,  Geoffrey S. Strongin

IPC分类号： H04K1/00 ,  H04L9/32 ,  H04N7/16

摘要： Methods for securing booting a personal computer system. One method includes establishing a secret between two or more devices and securing the secret in each of the two or more devices. Another method includes processing BIOS code instructions and accessing security hardware. The method also includes accessing a first device, locking the security hardware, and calling boot code. Another method includes reading a secret from a first location, storing the secret in a secure location different from the first location, and locking the first location. Another method includes requesting authentication for a device, receiving authentication for the device, and setting a timer associated with the device. Another method includes requesting authentication for a device, failing authentication for the device, and preventing access to the device upon failing authentication for the device.

摘要翻译： 用于确保启动个人计算机系统的方法。 一种方法包括在两个或更多个设备之间建立秘密，并且在两个或更多个设备中的每一个中确保秘密。 另一种方法包括处理BIOS代码指令和访问安全硬件。 该方法还包括访问第一设备，锁定安全硬件和调用引导代码。 另一种方法包括从第一位置读取秘密，将秘密存储在与第一位置不同的安全位置，并锁定第一位置。 另一种方法包括请求对设备的认证，接收设备的认证，以及设置与设备相关联的定时器。 另一种方法包括请求设备认证，设备认证失败，以及在设备认证失败时阻止对设备的访问。

公开(公告)号：US06791554B1

公开(公告)日：2004-09-14

申请号：US10034560

申请日：2001-12-27

申请人： James Mergard ,  Dale E. Gulick ,  Larry D. Hewitt

发明人： James Mergard ,  Dale E. Gulick ,  Larry D. Hewitt

IPC分类号： G06F1576

CPC分类号： G06T1/20

摘要： An I/O node for a computer system including an integrated graphics engine. An input/output node is implemented upon an integrated circuit chip. The I/O node includes a first transceiver unit, a second transceiver unit, a packet tunnel, a graphics engine and a graphics interface. The first transceiver unit may receive and transmit packet transactions on a first link of a packet bus and the second transceiver unit may receive and transmit packet transactions on a second link. The packet tunnel may convey selected packet transactions between the first and the second transceiver unit. The graphics engine may receive graphics packet transactions from the first transceiver unit and may render digital image information in response to receiving the graphics transactions. The graphics interface may receive additional graphics packet transactions from the first transceiver unit and may translate the additional graphics packet transactions into transactions suitable for transmission upon a graphics bus.

摘要翻译： 用于包括集成图形引擎的计算机系统的I / O节点。 输入/输出节点在集成电路芯片上实现。 I / O节点包括第一收发器单元，第二收发器单元，分组隧道，图形引擎和图形接口。 第一收发器单元可以在分组总线的第一链路上接收和发送分组交易，并且第二收发器单元可以在第二链路上接收和发送分组交易。 分组隧道可以在第一和第二收发器单元之间传送所选择的分组事务。 图形引擎可以从第一收发器单元接收图形分组交易，并且可以响应于接收到图形交易而呈现数字图像信息。 图形接口可以从第一收发器单元接收额外的图形分组事务，并且可以将附加的图形分组事务转换成适于在图形总线上传输的事务。