公开(公告)号：US07007300B1

公开(公告)日：2006-02-28

申请号：US09870890

申请日：2001-05-30

申请人： Frederick D. Weber ,  Dale E. Gulick ,  Geoffrey S. Strongin

发明人： Frederick D. Weber ,  Dale E. Gulick ,  Geoffrey S. Strongin

IPC分类号： H04K1/00 ,  H04L9/32 ,  H04N7/16

摘要： Methods for securing booting a personal computer system. One method includes establishing a secret between two or more devices and securing the secret in each of the two or more devices. Another method includes processing BIOS code instructions and accessing security hardware. The method also includes accessing a first device, locking the security hardware, and calling boot code. Another method includes reading a secret from a first location, storing the secret in a secure location different from the first location, and locking the first location. Another method includes requesting authentication for a device, receiving authentication for the device, and setting a timer associated with the device. Another method includes requesting authentication for a device, failing authentication for the device, and preventing access to the device upon failing authentication for the device.

摘要翻译： 用于确保启动个人计算机系统的方法。 一种方法包括在两个或更多个设备之间建立秘密，并且在两个或更多个设备中的每一个中确保秘密。 另一种方法包括处理BIOS代码指令和访问安全硬件。 该方法还包括访问第一设备，锁定安全硬件和调用引导代码。 另一种方法包括从第一位置读取秘密，将秘密存储在与第一位置不同的安全位置，并锁定第一位置。 另一种方法包括请求对设备的认证，接收设备的认证，以及设置与设备相关联的定时器。 另一种方法包括请求设备认证，设备认证失败，以及在设备认证失败时阻止对设备的访问。

公开(公告)号：US07149854B2

公开(公告)日：2006-12-12

申请号：US09870889

申请日：2001-05-30

申请人： Frederick D. Weber ,  Dale E. Gulick ,  Geoffrey S. Strongin

发明人： Frederick D. Weber ,  Dale E. Gulick ,  Geoffrey S. Strongin

IPC分类号： G06F12/00

CPC分类号： G06F21/74 ,  G06F21/53 ,  G06F21/575 ,  G06F21/72 ,  G06F21/79 ,  G06F21/85 ,  G06F2221/2107 ,  G06F2221/2141 ,  G06F2221/2147

摘要： A method and system for providing an external locking mechanism for memory locations. The memory includes a first plurality of storage locations configured with BIOS data and a second plurality of storage locations. The second plurality of storage locations includes a first plurality of blocks readable only in SMM and a second plurality of blocks readable in SMM and at least one operating mode other than SMM. The computer system includes a bus, a memory coupled to the bus, and a device coupled to access the memory over the bus. The memory includes a plurality of storage locations, divided into a plurality of memory units. The device includes one or more locks configured to control access to one or more of the plurality of memory units.

公开(公告)号：US07421525B2

公开(公告)日：2008-09-02

申请号：US10842296

申请日：2004-05-10

申请人： R. Stephen Polzin ,  Frederick D. Weber ,  Gerald R. Talbot ,  Larry D. Hewitt ,  Richard W. Reeves ,  Shwetal A. Patel ,  Ross V. La Fetra ,  Dale E. Gulick ,  Mark D. Hummel ,  Paul C. Miranda

发明人： R. Stephen Polzin ,  Frederick D. Weber ,  Gerald R. Talbot ,  Larry D. Hewitt ,  Richard W. Reeves ,  Shwetal A. Patel ,  Ross V. La Fetra ,  Dale E. Gulick ,  Mark D. Hummel ,  Paul C. Miranda

IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F12/00 ,  G11C5/06

CPC分类号： G06F13/4243 ,  G06F12/0215 ,  G06F12/0862 ,  G06F13/1626 ,  G06F2212/6022

摘要： A system including a host coupled to a serially connected chain of memory modules. In one embodiment, each of the memory modules includes a memory control hub for controlling access to a plurality of memory chips on the memory module. The memory modules are coupled serially in a chain to the host via a plurality of memory links. Each memory link may include an uplink for conveying transactions toward the host and a downlink for conveying transactions originating at the host to a next memory module in the chain. The uplink and the downlink may convey transactions using packets that include control and configuration packets and memory access packets. The memory control hub may convey a transaction received on a first downlink of a first memory link on a second downlink of a second memory link independent of decoding the transaction.

摘要翻译： 一种系统，包括耦合到串行连接的存储器模块链的主机。 在一个实施例中，每个存储器模块包括用于控制对存储器模块上的多个存储器芯片的访问的存储器控​​制集线器。 存储器模块通过多个存储器链路串联地连接到主机。 每个存储器链路可以包括用于向主机传送事务的上行链路和用于将在主机处发起的事务传送到链路中的下一个存储器模块的下行链路。 上行链路和下行链路可以使用包括控制和配置分组和存储器访问分组的分组来传送事务。 存储器控制集线器可以在第二存储器链路的第二下行链路上传送在第一存储器链路的第一下行链路上接收的事务，而与解码事务无关。

公开(公告)号：US07003676B1

公开(公告)日：2006-02-21

申请号：US09871084

申请日：2001-05-30

申请人： Frederick D. Weber ,  Dale E. Gulick

发明人： Frederick D. Weber ,  Dale E. Gulick

IPC分类号： G06F11/30 ,  H04L9/00

CPC分类号： G06F21/82 ,  G06F21/74 ,  G06F21/79

摘要： A method and system for overriding access locks on secure assets in a computer system. The system includes a processor and a device coupled to the processor. The device includes one or more sub-devices, one or more access locks, and an access lock override register that stores one or more access lock override bits, including a lock override bit. The one or more access locks are configured to prevent access to the one or more sub-devices when the one or more access locks are engaged. Access to the one or more sub-devices is not allowed when the lock override bit is set. The method includes requesting a memory transaction for one or more memory addresses and determining a lock status for the one or more memory addresses. The method also includes returning the lock status for the one or more memory addresses. The method may determine if the lock status for the one or more memory address can be changed. The method may change the lock status of the one or more memory addresses to allow the memory transaction.

摘要翻译： 用于覆盖计算机系统中安全资产上的访问锁的方法和系统。 该系统包括处理器和耦合到处理器的设备。 该设备包括一个或多个子设备，一个或多个访问锁和存储一个或多个访问锁覆盖位的访问锁覆盖寄存器，其包括锁倍增位。 所述一个或多个访问锁被配置为当所述一个或多个访问锁定被接合时防止访问所述一个或多个子设备。 锁定倍率位置1时，不允许访问一个或多个子设备。 该方法包括为一个或多个存储器地址请求存储器事务并确定一个或多个存储器地址的锁定状态。 该方法还包括返回一个或多个存储器地址的锁定状态。 该方法可以确定一个或多个存储器地址的锁定状态是否可以改变。 该方法可以改变一个或多个存储器地址的锁定状态以允许存储器事务。

公开(公告)号：US07096323B1

公开(公告)日：2006-08-22

申请号：US10256970

申请日：2002-09-27

申请人： Patrick Conway ,  Frederick D. Weber

发明人： Patrick Conway ,  Frederick D. Weber

IPC分类号： G06F13/14

CPC分类号： G06F12/082 ,  G06F2212/2515 ,  Y02D10/13

摘要： A computer system with a processor cache that stores remote cache presence information. In one embodiment, a plurality of presence vectors are stored to indicate whether particular blocks of data mapped to another node are being remotely cached. Rather than storing the presence vectors in a dedicated storage, the remote cache presence vectors may be stored in designated locations of a cache memory subsystem, such as an L2 cache, associated with a processor core. For example, a designated way of the cache memory subsystem may be allocated for storing remote cache presence vectors, while the remaining ways of the cache are used to store normal processor data. New data blocks may be remotely cached in response to evictions from the cache memory subsystem. In yet a further embodiment, additional entries of the cache memory subsystem may be used for storing directory entries to filter probe command and response traffic.

摘要翻译： 具有存储远程缓存存在信息的处理器高速缓存的计算机系统。 在一个实施例中，存储多个存在向量以指示映射到另一节点的特定数据块是否被远程高速缓存。 而不是将存在向量存储在专用存储器中，远程高速缓存存在向量可以存储在与处理器核心相关联的高速缓冲存储器子系统（例如L 2高速缓存）的指定位置。 例如，缓存存储器子系统的指定方式可被分配用于存储远程高速缓存存在向量，而高速缓存的剩余方式用于存储正常的处理器数据。 响应于来自高速缓冲存储器子系统的驱逐，可以远程高速缓存新的数据块。 在又一个实施例中，高速缓存存储器子系统的附加条目可以用于存储目录条目以过滤探测命令和响应流量。

公开(公告)号：US06370637B1

公开(公告)日：2002-04-09

申请号：US09370789

申请日：1999-08-05

申请人： Stephan G. Meier ,  Norbert Juffa ,  Frederick D. Weber ,  Stuart F. Oberman

发明人： Stephan G. Meier ,  Norbert Juffa ,  Frederick D. Weber ,  Stuart F. Oberman

IPC分类号： G06F938

CPC分类号： G06F9/30032 ,  G06F9/30192 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： A microprocessor with a floating point unit configured to efficiently allocate multi-pipeline executable instructions is disclosed. Multi-pipeline executable instructions are instructions that are not forced to execute in a particular type of execution pipe. For example, junk ops are multi-pipeline executable. A junk op is an instruction that is executed at an early stage of the floating point unit's pipeline (e.g., during register rename), but still passes through an execution pipeline for exception checking. Junk ops are not limited to a particular execution pipeline, but instead may pass through any of the microprocessor's execution pipelines in the floating point unit. Multi-pipeline executable instructions are allocated on a per-clock cycle basis using a number of different criteria. For example, the allocation may vary depending upon the number of multi-pipeline executable instructions received by the floating point unit in a single clock cycle.

摘要翻译： 公开了一种具有配置成有效地分配多流水线可执行指令的浮点单元的微处理器。 多管道可执行指令是不强制在特定类型执行管道中执行的指令。 例如，垃圾操作是多管道可执行的。 垃圾操作是在浮点单元的流水线的早期执行的指令（例如，在寄存器重命名期间），但是仍然通过用于异常检查的执行管线。 垃圾操作不限于特定的执行管道，而是可以通过浮点单元中的任何一个微处理器的执行流水线。 使用许多不同的标准，在每个时钟周期的基础上分配多流水线可执行指令。 例如，分配可以根据浮点单元在单个时钟周期中接收的多流水线可执行指令的数量而变化。

公开(公告)号：US5119481A

公开(公告)日：1992-06-02

申请号：US696291

申请日：1991-04-26

申请人： Steven J. Frank ,  Henry Burkhardt, III ,  Frederick D. Weber

发明人： Steven J. Frank ,  Henry Burkhardt, III ,  Frederick D. Weber

IPC分类号： G06F15/173 ,  H04L12/433

CPC分类号： H04L12/433 ,  G06F15/17337

摘要： A digital data processing apparatus includes a shift-register bus that transfers packets of digital information. The bus has a plurality of digital storage and transfer stages connected in series in a ring configuration. A plurality of processing cells, each including at least a memory element, are connected in a ring configuration through the bus, with each cell being in communication with an associated subset of stages of the bus. At least one processing cell includes a cell interconnect that performs at least one of modifying, extracting, replicating and transferring a packet based on an association, if any, between a datum identified in that packet and one or more data stored in said associated memory element. The cell interconnect responds to applied digital clock cycle signals for simultaneously transferring at least a selected packet through successive stages of the bus at a rate responsive to the digital clock cycle rate, while performing the modifying, extracting, replicating and transferring operation.

摘要翻译： 数字数据处理装置包括传送数字信息包的移位寄存器总线。 该总线具有以环形配置串联连接的多个数字存储和传送级。 每个包括至少一个存储器元件的多个处理单元通过总线以环形配置连接，每个单元与总线的相关分级子集通信。 至少一个处理单元包括单元互连，其执行基于在该分组中识别的数据与存储在所述相关联的存储器元件中的一个或多个数据之间的关联（如果有的话）修改，提取，复制和传送分组中的至少一个 。 小区互连响应所应用的数字时钟周期信号，用于在执行修改，提取，复制和传送操作的同时以响应于数字时钟周期速率的速率在总线的连续级中同时传送至少一个选定分组。

公开(公告)号：US5055999A

公开(公告)日：1991-10-08

申请号：US136930

申请日：1987-12-22

申请人： Steven J. Frank ,  Henry Burkhardt, III ,  Linda O. Lee ,  Nathan Goodman ,  Benson I. Margulies ,  Frederick D. Weber

发明人： Steven J. Frank ,  Henry Burkhardt, III ,  Linda O. Lee ,  Nathan Goodman ,  Benson I. Margulies ,  Frederick D. Weber

IPC分类号： G06F15/177 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/50 ,  G06F11/00 ,  G06F11/07 ,  G06F12/08 ,  G06F12/10 ,  G06F12/12 ,  H04L12/46 ,  H04L12/56

CPC分类号： G06F9/5016 ,  G06F11/004 ,  G06F11/0724 ,  G06F11/073 ,  G06F11/0766 ,  G06F11/0772 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0817 ,  G06F12/0833 ,  G06F12/10 ,  G06F12/1018 ,  G06F9/30003 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/30087 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3865 ,  G06F9/468 ,  G06F9/52 ,  H04L12/4637 ,  H04L45/04 ,  G06F12/126 ,  G06F2212/272

摘要： A multiprocessor digital data processing system comprises a plurality of processing cells arranged in a hierarchy of rings. The system selectively allocates storage and moves exclusive data copies from cell to cell in response to access requests generated by the cells. Routing elements are employed to selectively broadcast data access requests, updates and transfers on the rings.

公开(公告)号：US06446189B1

公开(公告)日：2002-09-03

申请号：US09323321

申请日：1999-06-01

申请人： Gerald D. Zuraski, Jr. ,  Frederick D. Weber ,  William A. Hughes ,  William K. Lewchuk ,  Scott A. White ,  Michael T. Clark

发明人： Gerald D. Zuraski, Jr. ,  Frederick D. Weber ,  William A. Hughes ,  William K. Lewchuk ,  Scott A. White ,  Michael T. Clark

IPC分类号： G06F1200

CPC分类号： G06F12/1054

摘要： A processor is presented including a cache unit coupled to a bus interface unit (BIU). Address signal selection and masking functions are performed by circuitry within the BIU rather than within the cache unit, and physical addresses produced by the BIU are stored within the TLB. As a result, address signal selection and masking circuitry (e.g., a multiplexer and gating logic) are eliminated from a critical speed path within the cache unit, allowing the operational speed of the cache unit to be increased. The cache unit stores data items, and produces a data item corresponding to a received linear address. A translation lookaside buffer (TLB) within the cache unit stores multiple linear addresses and corresponding physical addresses. When a physical address corresponding to the received linear address is not found within the TLB, the cache unit passes the linear address to the BIU. The BIU includes address translation circuitry, a multiplexer, and gating logic, and returns the physical address corresponding to the linear address to the cache unit. The cache unit stores the physical address and the linear address within the TLB. The processor may also include a programmable control register and a microexecution unit. Upon detecting a change in state of an external masking signal, the microexecution unit may flush the contents of the TLB and modify a masking bit within the control register to reflect a new state of the masking signal.

摘要翻译： 呈现包括耦合到总线接口单元（BIU）的高速缓存单元的处理器。 地址信号选择和屏蔽功能由BIU内的电路而不是在高速缓存单元内执行，而由BIU生成的物理地址存储在TLB内。 结果，从高速缓存单元内的临界速度路径消除了地址信号选择和屏蔽电路（例如，多路复用器和门控逻辑），从而允许高速缓存单元的操作速度增加。 高速缓存单元存储数据项，并产生与所接收的线性地址对应的数据项。 缓存单元内的翻译后备缓冲器（TLB）存储多个线性地址和对应的物理地址。 当在TLB内没有找到与接收到的线性地址对应的物理地址时，高速缓存单元将线性地址传递给BIU。 BIU包括地址转换电路，多路复用器和门控逻辑，并将对应于线性地址的物理地址返回到高速缓存单元。 高速缓存单元存储TLB内的物理地址和线性地址。 处理器还可以包括可编程控制寄存器和微执行单元。 在检测到外部屏蔽信号的状态变化时，微执行单元可以刷新TLB的内容并修改控制寄存器内的屏蔽位以反映掩蔽信号的新状态。

公开(公告)号：US06298438B1

公开(公告)日：2001-10-02

申请号：US09303513

申请日：1999-05-03

申请人： John S. Thayer ,  John G. Favor ,  Frederick D. Weber

发明人： John S. Thayer ,  John G. Favor ,  Frederick D. Weber

IPC分类号： G06F738

CPC分类号： G06F9/30072 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/3885 ,  G06F9/3887

摘要： A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.

摘要翻译： 提供多媒体扩展单元（MEU）用于执行各种多媒体类型操作。 MEU可以通过协处理器总线或本地CPU总线耦合到常规处理器。 MEU使用向量寄存器，向量ALU和操作数路由单元（ORU）来尽可能少地执行多媒体操作。 通过根据期望的算法流程图将操作数布置在向量ALU上来容易地执行复杂算法。 ORU使用MAU特有的向量指令对齐向量寄存器的分区插槽或子时隙内的操作数。 在ORU的输出端，矢量源或目标寄存器的操作数对可以很容易地在矢量ALU中路由和组合。 向量指令采用特殊的加载/存储指令与许多操作指令相结合，对对齐的操作数执行并发的多媒体操作。