公开(公告)号：US06857033B1

公开(公告)日：2005-02-15

申请号：US10034967

申请日：2001-12-27

申请人： Dale E. Gulick ,  Larry D. Hewitt ,  James Mergard

发明人： Dale E. Gulick ,  Larry D. Hewitt ,  James Mergard

IPC分类号： G06F3/14 ,  G06F13/38 ,  G06F13/42

CPC分类号： G06F13/4265 ,  G06F3/14

摘要： An I/O node for a computer system including an integrated graphics engine and integrated I/O hub. An input/output node that is implemented on an integrated circuit chip includes a transceiver unit, a graphics engine and an I/O hub. The transceiver unit may receive and transmit packets on a point-to-point link of a packet interface. The graphics engine may be coupled to receive graphics packets received by the transceiver unit and may render digital image information in response to receiving the graphics packets. The I/O hub may be coupled to receive I/O packets corresponding to packets received by the transceiver unit and may initiate bus cycles corresponding to the I/O packets upon a peripheral bus. The packet interface link may be a point-to-point HyperTransport™ link including a first and second set of uni-directional wires which may convey control and data packets over the same wires.

摘要翻译： 用于计算机系统的I / O节点，包括集成图形引擎和集成I / O集线器。 在集成电路芯片上实现的输入/输出节点包括收发器单元，图形引擎和I / O集线器。 收发器单元可以在分组接口的点对点链路上接收和发送分组。 图形引擎可以被耦合以接收由收发器单元接收的图形分组，并且可以响应于接收到图形分组而呈现数字图像信息。 I / O集线器可以被耦合以接收对应于由收发器单元接收的分组的I / O分组，并且可以在外围总线上启动对应于I / O分组的总线周期。 分组接口链路可以是包括可以通过相同线路传送控制和数据分组的第一和第二组单向导线的点对点HyperTransport TM链路。

公开(公告)号：US06791554B1

公开(公告)日：2004-09-14

申请号：US10034560

申请日：2001-12-27

申请人： James Mergard ,  Dale E. Gulick ,  Larry D. Hewitt

发明人： James Mergard ,  Dale E. Gulick ,  Larry D. Hewitt

IPC分类号： G06F1576

CPC分类号： G06T1/20

摘要： An I/O node for a computer system including an integrated graphics engine. An input/output node is implemented upon an integrated circuit chip. The I/O node includes a first transceiver unit, a second transceiver unit, a packet tunnel, a graphics engine and a graphics interface. The first transceiver unit may receive and transmit packet transactions on a first link of a packet bus and the second transceiver unit may receive and transmit packet transactions on a second link. The packet tunnel may convey selected packet transactions between the first and the second transceiver unit. The graphics engine may receive graphics packet transactions from the first transceiver unit and may render digital image information in response to receiving the graphics transactions. The graphics interface may receive additional graphics packet transactions from the first transceiver unit and may translate the additional graphics packet transactions into transactions suitable for transmission upon a graphics bus.

摘要翻译： 用于包括集成图形引擎的计算机系统的I / O节点。 输入/输出节点在集成电路芯片上实现。 I / O节点包括第一收发器单元，第二收发器单元，分组隧道，图形引擎和图形接口。 第一收发器单元可以在分组总线的第一链路上接收和发送分组交易，并且第二收发器单元可以在第二链路上接收和发送分组交易。 分组隧道可以在第一和第二收发器单元之间传送所选择的分组事务。 图形引擎可以从第一收发器单元接收图形分组交易，并且可以响应于接收到图形交易而呈现数字图像信息。 图形接口可以从第一收发器单元接收额外的图形分组事务，并且可以将附加的图形分组事务转换成适于在图形总线上传输的事务。

公开(公告)号：US07146510B1

公开(公告)日：2006-12-05

申请号：US10198637

申请日：2002-07-18

申请人： Frank P. Helms ,  Derrick R. Meyer ,  Larry D. Hewitt ,  Dale E. Gulick ,  William A. Hughes ,  Scott E. Swanstrom

发明人： Frank P. Helms ,  Derrick R. Meyer ,  Larry D. Hewitt ,  Dale E. Gulick ,  William A. Hughes ,  Scott E. Swanstrom

IPC分类号： G06F1/26 ,  G06F1/32

CPC分类号： G06F1/3209 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F1/3296 ,  G06F9/30083 ,  Y02D10/126 ,  Y02D10/151 ,  Y02D10/172

摘要： An integrated circuit is coupled to a communication link and to a separate signal line and includes programmable registers specifying communication link width and frequency. The integrated circuit responds to a change in the value of the signal line by changing the width and/or frequency of at least a portion of the communication link to the programmed value in response to a change in a logical value of the signal line, without the integrated circuit entering a reset state. The width and/or frequency may be changed during a POST routine or during system operation as part of a power management or other system function while maintaining its operational state.

摘要翻译： 集成电路耦合到通信链路和单独的信号线，并且包括指定通信链路宽度和频率的可编程寄存器。 通过将通信链路的至少一部分的宽度和/或频率响应于信号线的逻辑值的改变而改变为编程值，集成电路响应于信号线的值的变化，而没有 集成电路进入复位状态。 宽度和/或频率可以在POST程序期间或在系统操作期间作为功率管理或其他系统功能的一部分而改变，同时保持其操作状态。

公开(公告)号：US06697890B1

公开(公告)日：2004-02-24

申请号：US10034878

申请日：2001-12-27

申请人： Dale E. Gulick ,  Larry D. Hewitt

发明人： Dale E. Gulick ,  Larry D. Hewitt

IPC分类号： G06F1312

CPC分类号： G06F13/4247 ,  G06F13/4004

摘要： An I/O node for a computer system including an integrated I/O interface. An input/output node for a computer system that is implemented upon an integrated circuit includes a first transceiver unit, a second transceiver unit, a packet tunnel, a bridge unit and an I/O interface unit. The first transceiver unit may receive and transmit packet transactions on a first link of a packet bus. The second transceiver unit may receive and transmit packet transactions on a second link of the packet bus. The packet tunnel may convey selected packet transactions between the first and second transceiver units. The bridge unit may receive particular packet transactions from the first transceiver may transmit transactions corresponding to the particular packet transactions upon a peripheral bus. The I/O interface unit may receive additional packet transactions from the first transceiver unit and may transmit transactions corresponding to the additional packet transactions upon an I/O link.

摘要翻译： 一个包含集成I / O接口的计算机系统的I / O节点。 在集成电路上实现的用于计算机系统的输入/输出节点包括第一收发器单元，第二收发器单元，分组隧道，桥接单元和I / O接口单元。 第一收发器单元可以在分组总线的第一链路上接收和发送分组事务。 第二收发器单元可以在分组总线的第二链路上接收和发送分组事务。 分组隧道可以在第一和第二收发器单元之间传送所选择的分组事务。 桥接单元可以接收来自第一收发器的特定分组事务可以在外围总线上发送与特定分组事务相对应的事务。 I / O接口单元可以从第一收发器单元接收附加分组事务，并且可以在I / O链路上传送与附加分组事务相对应的事务。

公开(公告)号：US06385705B1

公开(公告)日：2002-05-07

申请号：US09702147

申请日：2000-10-30

申请人： James B. Keller ,  Dale E. Gulick ,  Larry D. Hewitt ,  Geoffrey Strongin

发明人： James B. Keller ,  Dale E. Gulick ,  Larry D. Hewitt ,  Geoffrey Strongin

IPC分类号： G06F1300

CPC分类号： G06F13/1621

摘要： A circuit and method is disclosed for preserving the order for memory requests originating from I/O devices coupled to a multiprocessor computer system. The multiprocessor computer system includes a plurality of circuit nodes and a plurality of memories. Each circuit node includes at least one microprocessor coupled to a memory controller which in turn is coupled to one of the plurality of memories. The circuit nodes are in data communication with each other, each circuit node being uniquely identified by a node number. At least one of the circuit nodes is coupled to an I/O bridge which in turn is coupled directly or indirectly to one or more I/O devices. The I/O bridge generates non-coherent memory access transactions in response to memory access requests originating with one of the I/O devices. The circuit node coupled to the I/O bridge, receives the non-coherent memory access transactions. For example, the circuit node coupled to the I/O bridge receives first and second non-coherent memory access transactions. The first and second non-coherent memory access transactions include first and second memory addresses, respectively. The first and second non-coherent memory access transactions further include first and second pipe identifications, respectively. The node circuit maps the first and second memory addresses to first and second node numbers, respectively. The first and second pipe identifications are compared. If the first and second pipe identifications compare equally, then the first and second node numbers are compared. First and second coherent memory access transactions are generated by the node coupled to the I/O bridge wherein the first and second coherent memory access transactions correspond to the first and second non-coherent memory access transactions, respectively. The first coherent memory access transaction is transmitted to one of the nodes of the multiprocessor computer system. However, the second coherent memory access transaction is not transmitted unless the first and second pipe identifications do not compare equally or if the first and second node numbers compare equally.

公开(公告)号：US07334123B2

公开(公告)日：2008-02-19

申请号：US10429132

申请日：2003-05-02

申请人： Dale E. Gulick ,  Geoffrey S. Strongin ,  Larry D. Hewitt

发明人： Dale E. Gulick ,  Geoffrey S. Strongin ,  Larry D. Hewitt

IPC分类号： H04L9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F21/74 ,  G06F21/85 ,  G06F2221/2105

摘要： A computer system including a bus bridge for bridging transactions between a secure execution mode-capable processor and a security services processor. The bus bridge may include a transaction source detector, a configuration header and control logic. The transaction source detector may receive a security initialization transaction performed as a result of execution of a security initialization instruction. Further, the transaction source detector may determine whether the secure execution mode-capable processor is a source of the security initialization transaction. The configuration header may provide storage of information associated with the security services processor. The control logic may determine whether the security services processor is coupled to the bus bridge via a non-enumerable, peripheral bus. The control logic may also cause the configuration header to be accessible during a boot-up sequence in response to determining that the security services processor is coupled to the non-enumerable, peripheral bus.

摘要翻译： 一种计算机系统，包括用于桥接安全执行模式处理器和安全服务处理器之间的事务的总线桥。 总线桥可以包括事务源检测器，配置头和控制逻辑。 事务源检测器可以接收由于执行安全初始化指令而执行的安全初始化事务。 此外，事务源检测器可以确定安全执行模式处理器是否是安全初始化事务的源。 配置头可以提供与安全服务处理器相关联的信息的存储。 控制逻辑可以确定安全服务处理器是否经由不可枚举的外围总线耦合到总线桥。 响应于确定安全服务处理器耦合到不可枚举的外围总线，控制逻辑还可以使得配置头在引导序列期间可访问。

公开(公告)号：US06199132B1

公开(公告)日：2001-03-06

申请号：US09098854

申请日：1998-06-17

申请人： Larry D. Hewitt ,  Dale E. Gulick

发明人： Larry D. Hewitt ,  Dale E. Gulick

IPC分类号： G06F1300

CPC分类号： G06F13/4213

摘要： A bus transfers information including isochronous and asynchronous data between a first and a second integrated circuit. The bus guarantees a minimum bandwidth to isochronous data and also tries to minimize latency for isochronous data. The bus transfers data in asynchronous priority mode during a first portion of a first time period, wherein asynchronous data is transferred preferentially over isochronous data. Transfers over the bus selectably switch to isochronous priority mode for a second portion of the first time period in order to guarantee transfer of a predetermined amount of isochronous data during the first time period, thus guaranteeing the minimum bandwidth to isochronous data.

摘要翻译： 总线在第一和第二集成电路之间传送包括同步和异步数据的信息。 总线保证了同步数据的最小带宽，并且还尝试最小化同步数据的延迟。 总线在第一时间段的第一部分期间以异步优先模式传输数据，其中异步数据优先通过同步数据传送。 总线上的传输可选择地切换到第一时间段的第二部分的等时优先级模式，以便保证在第一时间段期间传送预定量的同步数据，从而保证对同步数据的最小带宽。

公开(公告)号：US07421525B2

公开(公告)日：2008-09-02

申请号：US10842296

申请日：2004-05-10

申请人： R. Stephen Polzin ,  Frederick D. Weber ,  Gerald R. Talbot ,  Larry D. Hewitt ,  Richard W. Reeves ,  Shwetal A. Patel ,  Ross V. La Fetra ,  Dale E. Gulick ,  Mark D. Hummel ,  Paul C. Miranda

发明人： R. Stephen Polzin ,  Frederick D. Weber ,  Gerald R. Talbot ,  Larry D. Hewitt ,  Richard W. Reeves ,  Shwetal A. Patel ,  Ross V. La Fetra ,  Dale E. Gulick ,  Mark D. Hummel ,  Paul C. Miranda

IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F12/00 ,  G11C5/06

CPC分类号： G06F13/4243 ,  G06F12/0215 ,  G06F12/0862 ,  G06F13/1626 ,  G06F2212/6022

摘要： A system including a host coupled to a serially connected chain of memory modules. In one embodiment, each of the memory modules includes a memory control hub for controlling access to a plurality of memory chips on the memory module. The memory modules are coupled serially in a chain to the host via a plurality of memory links. Each memory link may include an uplink for conveying transactions toward the host and a downlink for conveying transactions originating at the host to a next memory module in the chain. The uplink and the downlink may convey transactions using packets that include control and configuration packets and memory access packets. The memory control hub may convey a transaction received on a first downlink of a first memory link on a second downlink of a second memory link independent of decoding the transaction.

摘要翻译： 一种系统，包括耦合到串行连接的存储器模块链的主机。 在一个实施例中，每个存储器模块包括用于控制对存储器模块上的多个存储器芯片的访问的存储器控​​制集线器。 存储器模块通过多个存储器链路串联地连接到主机。 每个存储器链路可以包括用于向主机传送事务的上行链路和用于将在主机处发起的事务传送到链路中的下一个存储器模块的下行链路。 上行链路和下行链路可以使用包括控制和配置分组和存储器访问分组的分组来传送事务。 存储器控制集线器可以在第二存储器链路的第二下行链路上传送在第一存储器链路的第一下行链路上接收的事务，而与解码事务无关。

公开(公告)号：US07308514B1

公开(公告)日：2007-12-11

申请号：US10647397

申请日：2003-08-25

申请人： Larry D. Hewitt ,  Dale E. Gulick

发明人： Larry D. Hewitt ,  Dale E. Gulick

IPC分类号： G06F13/38

CPC分类号： G06F13/4027

摘要： Computer system configuration resources include first and second control circuits in respective first and second integrated circuits. A communication link, which transfers data over a plurality of logical pipes, connects the two integrated circuits. Configuration of the link utilizes a link bridge that includes upstream (located closest to the CPU) configuration registers that are within the first control circuit and downstream ((located farthest from the CPU) configuration registers within the second control circuit. A link header, which includes upstream data for the first control circuit and down stream data for the second control circuit, is used to initialize the link. The upstream and downstream data may include information specifying the size of the communication link.

摘要翻译： 计算机系统配置资源包括在第一和第二集成电路中的第一和第二控制电路。 通过多个逻辑管道传送数据的通信链路连接两个集成电路。 链路的配置使用包括第一控制电路内的上游（位于最靠近CPU）的配置寄存器和第二控制电路（（位于距离CPU最远）配置寄存器）的链路桥接器，链路头 包括用于第一控制电路的上行数据和第二控制电路的下行数据用于初始化链路，上游和下行数据可以包括指定通信链路大小的信息。

公开(公告)号：US06557048B1

公开(公告)日：2003-04-29

申请号：US09431364

申请日：1999-11-01

申请人： James B. Keller ,  Derrick R. Meyer ,  Dale E. Gulick ,  Larry D. Hewitt

发明人： James B. Keller ,  Derrick R. Meyer ,  Dale E. Gulick ,  Larry D. Hewitt

IPC分类号： G06F1300

CPC分类号： G06F13/4059

摘要： A computer system is presented which implements a system and method for ordering input/output (I/O) memory operations. In one embodiment, the computer system includes a processing subsystem and an I/O subsystem. The processing subsystem includes multiple processing nodes interconnected via coherent communication links. Each processing node may include a processor executing software instructions. The I/O subsystem includes one or more I/O nodes serially coupled via non-coherent communication links. Each I/O node may embody one or more I/O functions (e.g., modem, sound card, etc.). One of the processing nodes includes a host bridge which translates packets moving between the processing subsystem and the I/O subsystem. One of the I/O nodes is coupled to the processing node including the host bridges. The I/O node coupled to the processing node produces and/or provides transactions having destinations or targets within the processing subsystem to the processing node including the host bridge. The I/O node may, for example, produce and/or provide a first transaction followed by a second transaction. The host bridge may dispatch the second transaction with respect to the first transaction according to a predetermined set of ordering rules. For example, the host bridge may: (i) receive the first and second transactions, (ii) dispatch the first transaction within the processing subsystem, and (iii) dispatch the second transaction within the processing subsystem dependent upon progress of the first transaction within the processing subsystem and the predetermined set of ordering rules.

摘要翻译： 提出了一种实现用于排序输入/输出（I / O）存储器操作的系统和方法的计算机系统。 在一个实施例中，计算机系统包括处理子系统和I / O子系统。 处理子系统包括通过相干通信链路互连的多个处理节点。 每个处理节点可以包括执行软件指令的处理器。 I / O子系统包括通过非相干通信链路串联耦合的一个或多个I / O节点。 每个I / O节点可以体现一个或多个I / O功能（例如，调制解调器，声卡等）。 其中一个处理节点包括一个主机桥，它转换在处理子系统和I / O子系统之间移动的数据包。 其中一个I / O节点耦合到包括主机桥的处理节点。 耦合到处理节点的I / O节点产生和/或提供具有处理子系统内包含主机桥的处理节点的目的地或目标的事务。 I / O节点可以例如产生和/或提供第一事务，随后是第二事务。 主桥可以根据预定的一组排序规则来分派关于第一事务的第二事务。 例如，主桥可以：（i）接收第一和第二事务，（ii）在处理子系统内调度第一事务，以及（iii）根据第一事务的进度在处理子系统内调度第二事务 处理子系统和预定的一套排序规则。